Selectable self-timed replacement for self-resetting circuitry

Details Selectable self-timed replacement for self-resetting circuitry Selectable self-timed replacement for self-resetting circuitry

1998-05-29

2000-10-17

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 95, 326 98, 326 96, 326 97, H03K 1900, H03K 19096

Patent

active

061337587

ABSTRACT:
A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.

REFERENCES:
patent: 5565798 (1996-10-01), Durham et al.
patent: 5790560 (1998-08-01), Durham et al.
patent: 5870411 (1999-02-01), Durham et al.
patent: 5912900 (1999-06-01), Durham et al.
patent: 5939898 (1999-08-01), Henkels et al.
patent: 6005416 (1999-12-01), Beakes et al.

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