Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-28
2010-10-12
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07814454
ABSTRACT:
A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.
REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5773856 (1998-06-01), Bearden et al.
patent: 6047469 (2000-04-01), Luna
patent: 6300651 (2001-10-01), Kato
patent: 6384464 (2002-05-01), Shin
patent: 6631470 (2003-10-01), Chang et al.
patent: 6727723 (2004-04-01), Shimizu et al.
patent: 6826637 (2004-11-01), Chang et al.
patent: 6834375 (2004-12-01), Stine et al.
patent: 6968525 (2005-11-01), Chang et al.
patent: 2003/0057566 (2003-03-01), Huang et al.
patent: 2003/0172363 (2003-09-01), Chauhan et al.
patent: 2005/0235242 (2005-10-01), Waizumi
patent: 2006/0068302 (2006-03-01), Rankin et al.
patent: 2006/0129962 (2006-06-01), Dinter et al.
patent: 2006/0190894 (2006-08-01), Jwalant et al.
patent: 2006/0195809 (2006-08-01), Cohn et al.
patent: 2007/0094633 (2007-04-01), Andreev et al.
patent: 2008/0054404 (2008-03-01), Ueshima
patent: 4256352 (1992-09-01), None
patent: 1020050034013 (2005-04-01), None
“Investigation on Device Characteristics of MOSFET transistor placed Under Bond Pad for High-Pin-Count SOC Applications”, IEEE Transactions on Components and Packaging Technologies, V. 27 #3 p. 452-460.
“Impedance Terminator For AC Testing Monolithic Chips”, R. Bove, E.M. Hubacher and A.D. Savkar International Business Machines Technical Disclosure Bulletin. vol. 15, No. 9, Feb. 1973, p. 2681-2682.
Song, “PCT International Search Report”, Application No. PCT/US2008/068452, Oct. 28, 2008, 13 pages.
Chou Anthony I.
Dufrene Brian M.
Dunn James S.
Lumbra Christopher H.
Narasimha Shreesh
Canale Anthony
Hoffman Warnick LLC
International Business Machines - Corporation
Kik Phallaka
LandOfFree
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