Select line architecture for magnetic random access memories

Details Select line architecture for magnetic random access memories Select line architecture for magnetic random access memories

2001-05-23

2002-12-03

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including magnetic element

C365S055000, C365S066000

Reexamination Certificate

active

06490217

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to random access memory systems, and more particularly relates to an architecture for improving a write margin within a magnetic random access memory (MRAM) device.
BACKGROUND OF THE INVENTION
Thin film magnetic random access memory (MRAM) has been investigated since the early 1950s. However, as described in the text “Computer Storage Systems and Technology,” by Richard E. Matick, John Wiley & Sons (1977), which is incorporated herein by reference, these memories were deemed to be impractical due to narrow write and read margins which eroded as device dimensions were scaled. By the early 1970s, semiconductor-based memories, such as dynamic random access memory (DRAM), promised a simpler more compact memory solution than magnetic core memories, the most prevalent random access memory (RAM) available at the time. By the late 1970s, almost all development and production activity related to MRAM had been abandoned.
Recently, a renewed interest in MRAM has been sparked by its application to the nonvolatile memory market. New memory devices, such as a magnetic tunnel junction (MTJ) device, which exhibits magneto resistance, overcame an earlier obstacle of inductive sensing. As summarized in Scheuerlein et al., “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell,”
ISSCC
2000, pp. 128-129, desirable characteristics of MTJ-based memories include high integration density, high speed, low read power, and soft error rate (SER) immunity.
FIG. 1
depicts a conventional MTJ-based MRAM architecture, as described in the aforementioned Scheuerlein et al. paper. Like conventional thin film RAM, MTJ-based MRAM uses an architecture in which memory cells
100
are placed at the cross-points of intersecting write word lines
104
and bit lines
106
. Reading of the memory cell
100
is simplified by the inclusion of a field effect transistor (FET)
102
connected to each memory cell for improved isolation. More particularly, a drain terminal of a given FET
102
is coupled to a cell
100
, a gate terminal of the given FET
102
is coupled to a corresponding read word line
108
, and a source terminal is coupled to ground. In conventional magnetic memory architectures, however, writing individual memory cells without also writing adjacent or other non-intended cells remains a problem.
Typically, writing a memory cell involves passing electrical currents simultaneously through a bit line and word line at the intersection of which an intended MTJ cell resides. The selected MTJ cell will experience a magnetic field which is the vector sum of the magnetic fields created by the word and bit line currents. All other MTJ cell that share the same bit line or word line as the selected MTJ cell will be half-selected and will thus be subjected to either bit line or word line magnetic fields, respectively. Since the magnitude of the vector sum of the word line and bit line fields is about forty-one percent (41%) larger than the individual word line or bit line fields, the selectivity of a selected MTJ cell over half-selected MTJ cells is poor, especially when the non-uniform switching characteristics of the MTJ cells are considered.
Variations in the shape or size of an MTJ cell can give rise to variations in magnetic thresholds of the MTJ cells which are so large that it is virtually impossible to write a selected cell without also arbitrarily switching some of the half-selected cells, thus placing the reliability and validity of the stored data in question. There may also be environmental or other factors, such as temperature and processing variations, that adversely impact the write select margin. Additionally, the spontaneous switching of an MTJ cell when it is subjected to repeated magnetic field excursions much smaller than its nominal switching field, an effect known as “creep,” narrows the acceptable write select margin even further thereby making the need for greater selectivity of individual MTJ cells even more imperative.
FIG. 2A
graphically depicts the magnetic selectivity of an ideal thin film magnetic memory cell along a hard magnetic axis (e.g., representing the word line field) and an easy magnetic axis (e.g., representing the bit line field), as described, for example, by E. C. Stoner and E. P. Wohlfarth in a paper entitled “A Mechanism of Magnetic Hysteresis in Heterogeneous Alloys,”
Royal Society of London Philosophical Transactions
, Ser. A240 (1948), which is incorporated herein by reference. Assuming that the word line and bit line currents generate fields along the hard magnetic axis at point
210
and the easy magnetic axis at point
230
, respectively, of the magnetic memory cell, the field (H
x
, H
y
) required to switch the magnetic state of the cell must equal or exceed the solid curve or boundary
200
. This curve
200
, known by those skilled in the art as a switching asteroid, satisfies the relation H
x
2/3
+H
y
2/3
=H
k
2/3
, where H
x
is the hard axis field, H
y
is the easy axis field and H
k
is an anisotropy field. A selected cell experiences magnetic fields outside the boundary of the switching asteroid
200
(e.g., corresponding to point
220
) which are large enough to write the magnetic cell to a state that aligns with the easy axis field direction. The state of a half-selected cell doesn't change since the magnetic fields acting on it (e.g., corresponding to points
210
and
230
) remain within the boundary of the switching asteroid
200
.
It is important to consider that, although depicted as a thin fixed boundary line, the switching asteroid
200
, in reality, may significantly change shape due to environmental conditions (e.g., temperature) or other factors (e.g., device processing variations). Variations between individual MTJ cells can substantially reduce the write select margin within the overall memory structure. Non-ideal physical characteristics often blur the distinction between half-selected and selected memory cells, wherein the half-selected cells could be written in a write operation intended only for the selected cells.
Hence a major hurdle to the realization of practical sub-micron MRAM architectures has been the problem of write selectivity. There is a need, therefore, in the field of magnetic memory devices and systems for improved write selection techniques which can be readily adapted to the conventional MRAM architecture described above as well as other alternative memory architectures.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a write architecture for use in a magnetic random access memory (MRAM) device that allows selection of individual memory cells in an array without adversely disturbing neighboring cells in the array and thus increasing the integrity of the data stored therein.
It is another object of the present invention to provide an improved write selection architecture and methodology for MRAM that is compatible with conventional MRAM devices.
It is yet another object of the present invention to provide a write selection architecture for MRAM that utilizes a substantially reduced bit line current, resulting in lower overall system power consumption.
It is a further object of the present invention to provide a write selection architecture for MRAM that has a substantially increased acceptable write disturb margin and is thus less sensitive to magnetic cell mismatches, process variations and other environmental factors within an MRAM array.
Advantageously, the present invention provides an improved write selection architecture and methodology for use with a magnetic memory device that not only allows selection of individual memory cells in an array without adversely disturbing neighboring cells in the array, but also reduces the power consumed in the write operation and the overall sensitivity of the circuit to device mismatches, process variations and other environmental factors.
In accordance with one aspect of the present invention, an improved architecture for

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