Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2000-10-20
2002-12-03
VerSteeg, Steven H. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S298120, C204S298080, C204S298090, C204S298160
Reexamination Certificate
active
06488822
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and system for plasma-assisted processing of micro-electronic devices and, more particularly, to a system and method using a segmented-target cathode for performing ionized physical-vapor deposition processes, such as those that are utilized to produce semiconductor data storage, flat-panel display, photovoltaic and other devices used in electronic and information systems.
BACKGROUND OF THE INVENTION
Plasma-assisted physical-vapor deposition (PVD) using various sputtering target materials is commonly used in thin-film fabrication technology for manufacturing of semiconductor, data storage, flat-panel display, and photovoltaic devices. Plasma sputtering is the most important and widely used thin-film deposition fabrication technique. In semiconductor integrated circuit (IC) manufacturing, PVD processes are used to deposit contact/via barrier (e.g., TiN or TaN) and glue (e.g., Ti) layers as well as metallization materials (e.g., Al or Cu). State-of-the-art semiconductor technologies for producing high-performance logic devices such as microprocessor chips employ four to six levels of metal interconnects. Current salicided CMOS technologies with four levels of interconnects may use (a) one PVD step (e.g., Ti deposition) to form self-aligned silicide (i.e., salicide), (b) two PVD steps to deposit Ti and TiN layers at the contact level, (c) one PVD step to deposit the first level of interconnect (typically Al, plus 1% Si, and 0.5% Cu), (d) one PVD step to deposit an anti-reflection coating (ARC) layer to facilitate the interconnect patterning process, and (e) up to nine additional PVD process steps to form the three additional interconnect levels and associated via liner and barrier layers, as well as ARC layers. This process description illustrates that advanced semiconductor IC manufacturing technologies with multiple levels of interconnect can often require numerous PVD process steps, some with stringent step coverage and bottom coverage requirements in order to produce continuous coverage over high-aspect ratio contact and via structures.
The performance, reliability, and yield of the multilevel interconnects strongly influence the reliability and manufacturing yield of semiconductor chips, such as high-performance microprocessors. As a result, PVD fabrication processes play a significant role in semiconductor integrated circuits, since they influence all significant multilevel interconnect performance and reliability parameters.
Existing commercial PVD technologies usually employ DC or RF or pulsed DC (AC) magnetron sputtering in vacuum processing chambers. A typical commercial PVD module includes a single-substrate (single-wafer) vacuum process chamber (preferably designed as a cluster tool module), a temperature-controlled (with an option to apply biased electrical power) chuck to hold the substrate, and a sputter target (or magnetron cathode) that contains the desired material. DC (or pulsed DC) magnetron plasma excitation (with DC power levels up to 20 kW and higher) is usually used for sputter deposition of electrically conductive materials such as Al, Ti, Co and TiN. RF magnetron (or pulsed DC) sputtering is usually used for sputter deposition of electrically insulating (or resistive) materials. RF diode sputtering (as opposed to magnetron PVD sputtering) is the preferred choice for sputter deposition of some magnetic and insulating materials for applications such as thin-film head fabrication.
Each of these PVD methods generates a plasma from an inert plasma gas an sustains the plasma near the target area. The target material atoms or molecules are then sputtered from the target surface and a fraction of them is deposited on the device substrate. Sputter etching of the target surface occurs due to energetic argon ion or another suitable ionized gas (such as xenon) species. During the sputtering process, the sputtered species (mostly neutrals) are emitted within the vacuum chamber plasma environment over a wide range of spatial angles and a portion of the sputtered flux deposits on the device substrate. Other sputtering processes, such as reactive sputtering processes, use nitrogen or oxygen or another reactive gas, instead of, or in addition to, an inert gas within the vacuum processing chamber. Reactive magnetron sputtering processes that, deposit TiN layers from elemental Ti targets illustrate an example of this technique.
In general, the flux of the sputter atoms or species that the PVD target material emits has a relatively broad angular distribution. Similarly, the sputter flux of species arriving at the substrate surface has a relatively broad spatial distribution angle. This broad spatial distribution angle does not usually present a problem in applications involving substrates without high-aspect-ratio features.
However, some semiconductor device manufacturing applications involve substrates with high-aspect-ratio features. These applications require some degree of spatial filtering or collimation for the sputter species. A broad angular distribution of the PVD flux implies poor collimation or a low degree of collimation, whereas a narrow angular distribution relative to the perpendicular axis indicates a higher degree of PVD collimation. For instance, semiconductor interconnect applications require collimated sputtering for deposition of the contact and via liner/glue and barrier layers (e.g. Ti/TiN) when using high-aspect-ratio (e.g., on the order of ≧3:1) contacts and vias due to the bottom and sidewall coverage requirements. For a contact/via hole of width (or diameter) W and height H, the following parameters can be defined:
A
.
R
.
=
Δ
H
W
(
aspect
ratio
)
Bottom
Coverage
=
Δ
t
b
d
Sidewall
Coverage
=
Δ
t
s
d
(
step
coverage
)
where d is the thickness of sputtered material layer on extended flat top surfaces, t
b
is the sputtered material thickness at the bottom of the hole, and t
s
is the thickness of the sputtered material on the hole sidewall at mid height.
In conventional PVD processes without any built-in sputtering-collimation feature, the bottom coverage and sidewall coverage of the sputter deposited material degrades significantly as the microstructure aspect ratio increases. This degradation becomes increasingly worse for microstructure aspect ratios of greater than ~3:1. As a result, for applications requiring good (e.g., ≧25%) bottom coverage and sidewall coverage (e.g., ≧50%), existing PVD technologies use a collimator plate placed between the PVD target or cathode assembly and the substrate inside the vacuum chamber.
The collimator plate, usually made of aluminum or titanium, consists of an array of circular or hexagonal closely packed holes that typically have an aspect ratio of 1:1 or higher. The collimator plate operates as a spatial filter to reduce the angular distribution of the sputter flux species arriving at the substrate. The degree of collimation increases (thus decreasing the angular distribution of the sputter flux species at the substrate) as the collimator plate hole aspect ratio increases. Although physical collimation via a fixed collimator plate is extensively practiced in commercial PVD processes for semiconductor contact/via glue/liner and barrier deposition, it has a number of disadvantages.
First of all, a trade off exists between the sputter deposition rate (throughput) and the degree of collimation. In other words, higher degrees of collimation require collimators with higher aspect ratios resulting in a reduced deposition rate on the substrate. This trade-off in physically collimated PVD systems presents a significant throughput limitation. Secondly, the collimator becomes gradually coated with the sputtering material. This can result in particulate generation within the PVD vacuum chamber. Moreover, the coating creates a non-uniform blockage of the collimator holes that ca
Gray Cary Ware & Freidenrich LLP
Veecoleve, Inc.
VerSteeg Steven H.
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