Segmented on-chip memory and requester arbitration

Details Segmented on-chip memory and requester arbitration Segmented on-chip memory and requester arbitration

2005-04-15

2008-12-02

Myers, Paul R (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Decentralized arbitrating

C370S913000, C370S338000, C711S209000

Reexamination Certificate

active

07461191

ABSTRACT:
A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting access to the on-chip memory. The requesters are on-chip circuits and/or external devices. The arbitration unit determines a memory circuit to be accessed for each request that is received from a requester. The determination may be based on a software configurable arbitration scheme. The memory segments may form a bank of single-port SRAM (Static Random Access Memory) devices.

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