Segmented non-volatile memory array with multiple sources having

Details Segmented non-volatile memory array with multiple sources having Segmented non-volatile memory array with multiple sources having

1996-02-23

1997-11-11

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

36518511, 36518513, 36518529, 365218, G11C 700

Patent

active

056871171

ABSTRACT:
A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

REFERENCES:
patent: 5033023 (1991-07-01), Hsia et al.
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5384742 (1995-01-01), Miyakawa et al.

Affiliated with

Also associated with

Rating

Segmented non-volatile memory array with multiple sources having does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Segmented non-volatile memory array with multiple sources having, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segmented non-volatile memory array with multiple sources having will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1234117