Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2005-07-05
2005-07-05
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S063000, C365S185110, C365S185130, C365S185180, C365S185290
Reexamination Certificate
active
06914813
ABSTRACT:
A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
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Chevallier Christophe J.
Lakhani Vinod C.
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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