Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1997-09-12
2002-06-18
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S185050, C365S185110, C365S185130
Reexamination Certificate
active
06407941
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory systems and in particular t a segmented non-volatile memory array having multiple sources so that blocks of the array can be erased separately and having improved source line decode circuitry.
BACKGROUND ART
Non-volatile semiconductor memory systems have become increasingly popular, including flash memory systems.
FIG. 1
is a simplified diagram of the cross-section of a typical flash memory cell
10
. Cell
10
is an N-channel device formed in a P-type substrate
12
. An N-type drain region
14
is formed in substrate
12
as is an N-type source region
16
. Source region
16
includes an N-type region
16
A formed in the substrate
12
having a an N+-type region
16
B formed inside region
16
A so as to form a graded source region
16
.
The drain and regions source
14
and
16
are spaced apart from one another so as to form a channel region
12
A in the substrate intermediate the two regions. A floating gate
18
is disposed above the channel region
12
A and a control gate
20
is disposed above the floating gate
18
. The floating gate is separated from the channel region
12
A by a thin (100 Å) gate oxide layer
22
. The floating and control gates
18
and
20
are typically both formed from doped poly silicon. The control gate
20
is separated from the floating gate
18
by an interpoly dielectric layer
24
. Other than being capacitively coupled to other elements of cell
10
, the floating gate
18
is electrically isolated from the rest of the cell.
Table 1 below shows typical conditions for performing program, read and erase operations (two approaches) on flash cell
10
.
TABLE 1
SOURCE
DRAIN
CONTROL
OPERATION
(V
S)
(V
D
)
GATE (V
G)
READ
ground
+1.5 volts
+5 volts
PROGRAM
ground
+6 volts
+12 volts
ERASE 1
+12 volts
float
ground
ERASE 2
+5 volts
float
−10 volts
If cell
10
is in an erased state, the cell will have a threshold voltage, called an erased threshold voltage, which is typically approximately +2 volts. If the cell is in a programmed state, the cell will have a programmed threshold voltage of typically approximately +6 volts. In a read operation, the control-gate-to-source voltage of the cell is +5 volts as can be seen from Table 1, above. The drain
14
will be connected to a small positive voltage of typically +1.5 volts and the source
16
is grounded. Thus, if the cell
10
is in a programmed state, the cell will not conduct current in the read operation since the gate-to-source voltage of +5 volts is less than the programmed threshold voltage of +6 volts. If the cell is in an erased state, the gate to source voltage will exceed the erased threshold voltage so that the cell will conduct current. The presence or absence of cell current in a read operation is detected by a sense amplifier so that the state of the cell can be determined.
In order to program the flash cell
10
, Table 1 indicates that the source
16
is grounded and the drain
14
is connected to +6 volts. The control gate
20
is connected to a high voltage such as +12 volts. The combination of conditions will cause electrons to travel from the source
16
towards the drain
14
. Some of these electrons will possess sufficient energy to pass through the gate oxide
22
towards the positive voltage on the control gate
20
. Those electrons, sometimes referred to as hot electrons, will be deposited on the floating gate
18
and will remain there until the cell
10
is erased. The presence of electrons on the floating gate
18
will tend to increase the threshold voltage of the cell, as previously noted.
Table 1 depicts two approaches for erasing a cell. The first approach (Erase 1), a cell is erased by floating the drain
14
and applying a large positive voltage, such as +12 volts, to the source
16
. The control gate
20
is grounded. This combination causes electrons stored on the floating gate
18
to pass through the thin gate oxide
22
and to be transferred to the source
16
. The physical mechanism for the transfer is commonly referred to as Fowler Nordheim tunneling.
The above conditions for erasing a cell (Erase 1) have been viewed by others as disadvantageous in that the large positive voltage (+12 volts) applied to the source region is difficult to implement in an actual memory system. First, the primary supply voltage V
CC
in a typical integrated circuit memory system is +5 volts and is provided by an external power supply such as a battery. Thus, one approach would be to include a charge pump on the memory integrated circuit which is also powered by the primary supply voltage VCC. However, a typical integrated circuit memory system may include a million or more cells all or a very large group of which will be erased at the same time. Thus, the charge pump circuit must be capable of providing-relatively large amounts of current on the order of 20 to 30 milliamperes. This has been viewed by others as impractical thus necessitating the use of an a second external supply voltage for producing the +12 volts applied to the source region. This would typically preclude battery powered operation where multiple batteries, such as a +5 volt primary supply battery and a +12 volts battery, is not practical.
The application of the relatively high voltage of +12 volts has also been viewed as disadvantageous in that there was believed to be a tendency to produce high energy holes (“hot” holes) at the surface of the source region
16
near the channel region
12
a.
These positive charges were said to have a tendency to become trapped in the thin gate oxide
20
and eventually migrate to the floating gate and slowly neutralize any negative charge placed on the floating gate during programming. Thus, over time, the programmed state of the cell may be altered. Other deleterious effects due to the presence of holes have been noted, including the undesired tendency to program non-selected cells.
The above-described disadvantages of the erase conditions set forth in Table 1 (Erase 1) have been noted in U.S. Pat. No. 5,077,691 entitled FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION. The solution in U.S. Pat. No. 5,077,691 is summarized in Table 1 (Erase 2). A relatively large negative voltage ranging from −10 to −17 volts is applied to the gate
22
during an erase operation. In addition, the primary supply voltage V
CC
of +5 volts (or less) is applied to the source region
16
. The drain region
14
is left floating.
Although the source current remains relatively high, the voltage applied to the source is sufficiently low that the +5 volt primary supply voltage V
CC
can be used directly or the source voltage may be derived from the primary supply voltage using a series regulator or a resistive divider in combination with a buffer circuit. In either event, since the source voltage is equal to or less than the primary supply voltage, the large source currents required in erase operations can be provided without the use of charge pump circuitry. The high impedance control gate
20
of the flash cell draws very little current. Accordingly, the large negative voltage applied to the control gate
20
in the erase operation can be provided by a charge pump circuit. Thus, according to U.S. Pat. No. 5,077,691, only a single external power supply, the +5 volt supply for V
CC
, need be used.
In a flash memory system, the flash cells
10
are arranged in a cell array which typically includes several rows and several columns of cells. Each of the rows has an associated word line connected to the control gate
20
of the cells
10
located in the row. Each of the columns has an associate bit line connected to the drain
14
of each cell located in the column. The sources
16
of all of the cells of the array are usually connected in common, but as will be explained, the sources may be separately connected.
FIG. 2A
is a simplifie
Chevallier Christophe J.
Lakhani Vinod C.
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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