Segmented dataline scheme in a memory with enhanced full...

Details Segmented dataline scheme in a memory with enhanced full... Segmented dataline scheme in a memory with enhanced full...

2006-11-28

2006-11-28

Phan, Trong (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S230060, C365S189080

Reexamination Certificate

active

07142442

ABSTRACT:
A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.

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Xilinx, Inc., “The Programmable Logic Data Book 1998,” pp. 4-1 to 4-68, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124.

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