Segmented bus architecture (SBA) for electrostatic discharge (ES

Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

361 56, H02H 322

Patent

active

060468971

ABSTRACT:
A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.

REFERENCES:
patent: 4063274 (1977-12-01), Dingwall
patent: 4173022 (1979-10-01), Dingwall
patent: 4272881 (1981-06-01), Angle
patent: 4274193 (1981-06-01), Angle
patent: 4423431 (1993-12-01), Sasaki
patent: 4989057 (1991-01-01), Lu
patent: 5144519 (1992-09-01), Chang
patent: 5311391 (1994-05-01), Dungan et al.
patent: 5399507 (1995-03-01), Sun
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5477414 (1995-12-01), Li et al.
patent: 5530612 (1996-06-01), Maloney
patent: 5539327 (1996-07-01), Shigehara et al.
patent: 5565790 (1996-10-01), Lee
patent: 5726844 (1998-03-01), Smith
Naresh Tandan, "ESD Trigger Circuit", EOS/ESD Symposium, Section 3.3.1-3.3.5 (1994).
Voldman, et al., "Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors", EOS/ESD Symposium, pp. 43-61 (1995).
Amerasekera, et al., "Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes", IEDM, pp. 547-550 (1995).
Ramaswamy, et al., "EOS/ESD Analysis of High-Density Logic Chips", EOS/ESD Symposium, pp. 285-290 (1996).
Jean-Pierre Colinge, "Silicon-on-Insulator Technology: Materials to VLSI", Chpt. 4: SOI CMOS Technology, pp. 102-106, 1991 Kluwer Academic Publishers.
Stanley Wolf Ph.D., "Silicon Processing for the VLSI Era Vol. 2 ", Silicon Processing for the VLSI Era, pp. 72-75, 1990 Lattice Press.
William Palumbo et al., "Design and Characterication of Input Protection Networks for CMOS/SOS Applications", EOS/ESD Symposium Proceeding 1986, pp. 182-187.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Segmented bus architecture (SBA) for electrostatic discharge (ES does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Segmented bus architecture (SBA) for electrostatic discharge (ES, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segmented bus architecture (SBA) for electrostatic discharge (ES will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-371088

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.