Security features in interconnect centric architectures

Details Security features in interconnect centric architectures Security features in interconnect centric architectures

2011-06-14

2011-06-14

Baderman, Scott T (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07962786

ABSTRACT:
A method comprising: detecting a sub-system to be controlled in a reduced resource mode in a device having an interconnecting system architecture; sending a resource reducing request to an interconnect node of the sub-system, the interconnect node belonging to a first power/clock signal domain; and reducing resources of processing elements of the sub-system belonging to a second power/clock signal domain.

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MIPI Alliance System Power Management (SPM) Architectural Framework White Paper, Version 1.0; 2005 MIPI Alliance, Inc.; Retrieved from the Internet Jan. 14, 2008—http://www.mipi.org/docs/mipi-spm-framework-wp-2005.pdf; Figures 1-3, chapters 6.1-6.3, 8, 9.1, 10.2, and 10.3 (pp. 19-20, 22, 27 and 29-30).

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