Security chip architecture and implementations for...

Details Security chip architecture and implementations for... Security chip architecture and implementations for...

2005-11-29

2005-11-29

Song, Hosuk (Department: 2135)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Packet header designating cryptographically protected data

C713S181000, C713S189000

Reexamination Certificate

active

06971006

ABSTRACT:
An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

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