Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Security kernel or utility
Reexamination Certificate
1999-07-09
2004-02-17
Wright, Norman M. (Department: 2134)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Security kernel or utility
C713S162000
Reexamination Certificate
active
06694432
ABSTRACT:
FIELD OF THE INVENTION
The invention involves testing electronic components and, in particular, to securing data in a machine for testing electronic components.
BACKGROUND OF THE INVENTION
In general, a machine for testing electronic components includes the following three parts:
(1) a central processor unit (CPU) provided with storage means such as a hard disk, in which at least one file for the test to be performed is stored. The CPU constitutes a computer enabling an operator to start the test, to monitor certain parameters while the test is running, and to retrieve data at the end of the test. Test files include a truth table in which each column corresponds to one of the pins of a component under test and in which each line, also referred to as a “vector”, defines a configuration of logical 0 or 1 signals which are either stimuli to apply to certain pins, or the responses expected from stimuli applied to other pins;
(2) an electronic test unit connected to the CPU via a tester interface situated between the bus of the CPU and a transmission bus of the electronic test unit, and over which test vector files are transferred prior to execution from the hard disk of the CPU to the local memory of the electronic test unit. This operation of transferring test vector files is necessary because a test performed directly from the files stored on the hard disk would take far too long, given the time required to read the hard disk and the time required for transmitting the test vector files through the tester interface from the hard disk to the electronic test unit. The electronic test unit also has a timing generator for supplying testing events organized in a temporal sequence. A formatter serves to organize the vectors of the truth table in the time sequence received from the timing generator so as to constitute a set of logic signals complying with the successive operations that are to be performed during the test; and
(3) a test head in which the electronic components that are to be tested are placed, and having an electronic link whose function is to put into analog form the logical stimuli as a function of the technology and the logic used by the components, and conversely, to put into logic form the responses of the components to the applied stimuli.
At present, test vector files are stored in unencrypted form on the hard disk of the CPU. The contents thereof, and in particular the test vectors, can thus easily be accessed from the CPU of the test machine and can be copied onto any medium, and in particular onto a floppy disk. In addition, the operation of the test machine includes a debug mode for reading or modifying the local memory after it has been loaded. In this particular mode, it is thus also possible to access the files loaded into the local memory, and thus to access the test vectors.
Unfortunately, test vectors may contain sensitive data, for example, the codes of bank cards, the on-board software, e.g. game software protected by copyright, or indeed passwords giving access to components for reading installed software that is under test.
SUMMARY OF THE INVENTION
An object of the present invention is to secure data which is stored in an electronic component test machine having a CPU provided with storage means and a local memory connected to the storage means via a transmission bus.
Another object of the invention is to limit and control access to the test vector files during the various stages of a test.
These and other objects are accomplished in accordance with one aspect of the invention which is directed to a method which utilizes at least one file of test vectors. Data contained in the file of test vectors is encrypted by encrypting-decrypting means, and the encrypted test vector file is stored in the storage means of the central processor unit. Prior to each test, the encrypted test vector file is loaded into the local memory via the transmission bus. The encrypted data of the test vector file is decrypted, and the component test is performed therewith.
Thus, the invention makes it possible to prevent access to sensitive data while the test vector file is installed in the storage means, and in particular the hard disk of the CPU.
Another aspect of the invention is directed to an apparatus for securing data in an electronic component test machine which includes a central processor unit provided with storage means. A local memory is connected to the storage means via a transmission bus. The apparatus includes a means for providing at least one file of test vectors, means for encrypting data contained in the file of test vectors, means for storing the encrypted test vector file in the storage means of the central processor unit, means for loading the encrypted test vector file into the local memory via the transmission bus prior to each test, means for decrypting the encrypted data of the test vector file, and means for performing the test with the test vector file outputted by the decrypting means.
Still another aspect of the invention is directed to an apparatus for securing a file of test vectors utilized in an electronic component test machine having (i) a central processing unit with a storage memory storing an encrypted file of test vectors, (ii) a local memory coupled to the storage memory, and (iii) a component test unit coupled to an output of the local memory for performing a component test. The apparatus includes a decrypting device and a communication bus coupling the storage memory to the local memory and coupling the decrypting device to the local memory. A security interface controls communication on the bus between the decrypting device and the local memory to enable decryption of an encrypted file of test vectors previously loaded into the local memory from the storage memory and then storing the resulting unencrypted file in the local memory. The security interface blocks access to the local memory by the central processing unit while the local memory contains an unencrypted file of test vectors.
In accordance with a specific feature of the invention, it is possible, even after the test vector file has been loaded, to access the local memory and thus the non-encrypted sensitive data, by using the debug mode which is intended to enable an operator to take action if errors appear while a test is being executed. The invention normally prevents a read or modify access to the local memory after the encrypted data of the test vector file is decrypted. Nevertheless, if it is desired to enable an operator to read or modify the local memory for debug purposes, e.g. while developing the program or while looking for a problem in a test, it is advantageous to authorize such access to the local memory for reading or modification purposes, and this is accomplished by presenting an access authorization.
In a particular embodiment of the invention, the encryption-decryption is performed by an encrypting-decrypting means which is an electronic chip card containing a secret key and an encrypting-decrypting algorithm. The level of security obtained in this way is very high since, firstly, the secret key embedded in the memory of the card can be discovered neither by the person who encrypted the sensitive data nor by the operator and, secondly, it is never transmitted to the test machine since it is the card which does its own decrypting.
Similarly, provision can be made for the access authorization to be contained in an electronic chip card which is, in general, different from the encrypting-decrypting card, but that is provided with all of the access privileges needed for a debug mode.
REFERENCES:
patent: 4864494 (1989-09-01), Kobus, Jr.
patent: 5553144 (1996-09-01), Almquist et al.
patent: 6473861 (2002-10-01), Stokes
Gazounaud Yann
Wach Max
Schlumberger Systemes
Wright Norman M.
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