Secure store implementation on common platform storage subsystem

Details Secure store implementation on common platform storage subsystem Secure store implementation on common platform storage subsystem

1997-12-19

2000-03-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

714 6, 714 22, 710 57, 710 17, C06F 1110

Patent

active

060353473

ABSTRACT:
A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up. The NV-Buffer is a fast drain buffer and is equipped with a backup power source sufficient to hold up a power needed to transfer the data when the power is down.

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