Secure processor architecture for use with a digital rights...

Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Security kernel or utility

Reexamination Certificate

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C726S027000

Reexamination Certificate

active

08065521

ABSTRACT:
A secure processor is operable in normal and preferred modes, and includes a security kernel instantiated when the processor enters into preferred mode and a security key accessible by the security kernel during preferred mode. The security kernel employs the accessed security key to authenticate a secure application, and allows the processor to be trusted to keep hidden a secret of the application. To instantiate the application, the processor enters preferred mode where the security key is accessible, and instantiates and runs the security kernel. The security kernel accesses the security key and applies same to decrypt a key for the application, stores the decrypted key in a location where the application will expect same, and instantiates the application. The processor then enters the normal mode, where the security key is not accessible.

REFERENCES:
patent: 5029206 (1991-07-01), Marino et al.
patent: 5502766 (1996-03-01), Boebert et al.
patent: 5812857 (1998-09-01), Nelson et al.
patent: 5892900 (1999-04-01), Ginter et al.
patent: 5991399 (1999-11-01), Graunke et al.
patent: 6138236 (2000-10-01), Mirov et al.
patent: 6253193 (2001-06-01), Ginter et al.
patent: 6475180 (2002-11-01), Peterson et al.
patent: 6505300 (2003-01-01), Chan et al.
patent: 6527638 (2003-03-01), Walker et al.
patent: 6557104 (2003-04-01), Vu et al.
patent: 6560581 (2003-05-01), Fox et al.
patent: 6564995 (2003-05-01), Montgomery
patent: 6574609 (2003-06-01), Downs et al.
patent: 6581162 (2003-06-01), Angelo et al.
patent: 6615349 (2003-09-01), Hair
patent: 2001/0005201 (2001-06-01), Digiorgio et al.
patent: 2006/0130130 (2006-06-01), Kablotsky
patent: 2008/0298581 (2008-12-01), Murase et al.
patent: 2008/0301440 (2008-12-01), Plouffe et al.
patent: 2008/0301468 (2008-12-01), Murase et al.
Anderson, R. et al., “Tamper Resistance—A Cautionary Note,”Proc. of the 2ndUSENIX Workshop on Electronic Commerce, Oakland, California, Nov. 1996, 1-11.
Clark, P. et al., “BITS: A Smartcard Protected Operating System,”Comm. Of the ACM, Nov. 1994, 37(11), 66-70 and 94.
Gilmont, T. et al., “An Architecture of Security Management Unit for Safe Hosting of Multiple Agents,”IS&T/SPIE Conf. On Security and Watermarking of Multimedia Contents, San Jose, California, Jan. 1999, SPIE vol. 3657, 472-483.
Schneck, P. B., “Persistent Access Control to Prevent Piracy of Digital Information,”,Proc. of the IEEE, Jul. 1999, 87(7), 1239-1250.

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