Secure power-on reset engine

Details Secure power-on reset engine Secure power-on reset engine

2011-02-22

2011-02-22

Suryawanshi, Suresh K (Department: 2115)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C726S034000, C327S142000

Reexamination Certificate

active

07895426

ABSTRACT:
A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

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