Secure EEPROM memory comprising an error correction circuit

Details Secure EEPROM memory comprising an error correction circuit Secure EEPROM memory comprising an error correction circuit

2007-02-13

2007-02-13

Beausoliel, Robert W. (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

10317005

ABSTRACT:
An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.

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Harvey F. Hoffman et al., An Error Detection and Management Approach for Nonvolatile Electrically Ersable and Programmable Read Only Memory (EEPROM) Systems United Technologies Norden Systems, 0-7803-1290-2Q3 $3.00 01993 IEEE.

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