Secure computer with bus monitoring system and methods

Details Secure computer with bus monitoring system and methods Secure computer with bus monitoring system and methods

1998-06-22

2000-10-31

Iqbal, Nadeem

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

714 44, G06F 1100

Patent

active

061417572

ABSTRACT:
A secure computer system (100) includes a host processor (105) for communicating a datum to a trusted bus (101). A bridge (125) connects the trusted bus (101) to an untrusted bus (102). The bridge (125) conveys the datum from the trusted bus (101) to the untrusted bus (102). A bus access monitor (200) is coupled to the trusted bus (101) and the untrusted bus (102). The bus access monitor (200) performs a method (1000, FIG. 10) for securely monitoring the untrusted bus (102), and asserting an alarm signal when address information associated with the datum fails to compare with predetermined address information. Additionally, the host processor (105) performs a method (300, FIG. 3) for self-testing the bus access monitor.

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