Sectorless flash memory architecture

Details Sectorless flash memory architecture Sectorless flash memory architecture

2000-03-03

2003-12-09

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S165000, C365S185110, C365S185130, C365S185290, C365S185330, C365S189040, C365S230030, C365S230060

Reexamination Certificate

active

06662263

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to non-volatile memory and to systems for storage of blocks of information.
2. Description of Related Art
A conventional non-volatile semiconductor memory such as a Flash memory includes one or more arrays of memory cells.
FIG. 1A
shows a conventional architecture for a Flash memory
100
including an array
110
. The memory cells in array
110
are arranged in rows and columns and connected together by row lines
112
and column lines
113
(also referred to as word lines
112
and bit lines
113
). Each row line
112
connects to the control gates of memory cells in an associated row, and each column line
113
connects to the drains of memory cells in an associated column. Flash memory array
110
is further divided into multiple sectors
115
. Each sector
115
contains one or more columns of memory cells and has an associated source line
114
connected to the sources of the memory cells in the sector
115
. Further associated with each memory array
110
are a row decoder
120
, a column decoder
130
, and a source decoder
140
that respectively connect to row lines
112
, column lines
113
, and source lines
114
of the array
110
. Drivers (not shown) associated with row decoder
120
, column decoder
130
, and source decoder
140
bias row lines
112
, column lines
113
, and source lines
114
as required for erase, write, and read operations.
FIG. 1B
shows another architecture for a Flash memory array
110
′. Array
110
′ is similar to array
110
(
FIG. 1A
) but has row-based sectors
115
′, instead of column based sectors. Each sector
115
′ includes one or more rows of memory cell a source line
114
′ connected to the sources of the memory cells in the sector
115
′. A source decoder
140
′ connects to and controls the voltage levels on source lines
114
′ for erase, write, and read operations.
The memory arrays
110
and
110
′ commonly store blocks of data. For example, a digitally encoded music player such as an MP
3
music player can employ array
110
or
110
′ to store data representing music or songs. The data for each song is stored in one or more sectors
115
or
115
′, and each sector
115
or
115
′ only stores data from one song. This arrangement permits a user to erase one song by erasing the sector or sectors associated with the song. The data associated with other songs, being stored in separate sectors, is not erased. A user can thus keep a favorite song while changing other songs. One drawback of this data arrangement is the wasted storage capacity resulting when data for a song only partly fills a sector so that some memory cells store no data. Sectors can be made smaller to reduce the average amount of wasted data storage. But, smaller sectors require a Flash memory to include more sectors for the same amount of storage, and the increase in the number of sectors increases circuit overhead. Accordingly, providing the greatest possible effective storage capacity per integrated circuit area requires balancing wasted memory cells in large sectors against increased overhead for small sectors.
Another concern or drawback of the conventional Flash memory architectures is the accumulation of disturbances of the threshold voltages of memory cells. With either array
110
or
110
′, row decoder
120
and column decoder
130
respectively apply signals to a selected row line and a selected column line to write to or read from a selected memory cell. For a write operation, the voltages on the selected row and column lines are high and combine to change the threshold voltage of the selected memory cell, thereby writing a data value. The high row and column voltages can disturb the threshold voltages of unselected memory cells connected to the selected row line or the selected column line. These disturbances of the threshold voltages (i.e., write disturbs) can accumulate over time.
For an erase operation, source decoder
140
or
140
′ and row decoder
120
establish in a selected sector a voltage difference between the control gates and the sources of the memory cells while the drains float. The voltage difference causes Fowler-Nordheim tunneling that lowers the threshold voltages of the memory cells in the selected sector, to an erased state. Typically, the source decoder applies a positive voltage to the source line
114
or
114
′ for a selected sector, and row decoder
120
applies ground or a negative voltage to the row lines associated with the selected sector. For array
110
, row lines
112
connect to memory cells in sectors
115
not being erased. Accordingly, erasing the selected sector can disturb the threshold voltages of memory cells in other sectors of the array
110
. These disturbances of the threshold voltages (i.e., erase disturbs) can accumulate over time.
Particular problems arise if data remains in some sectors while other sectors of the array are repeatedly erased and programmed. In this case, the accumulated write and erase disturb can change the threshold voltages of memory cells in sectors storing long term data. Such disturbance can become intolerable in a multi-bit-per-cell memory. In a multi-bit-per-cell memory, each memory cell stores N bits of information and requires 2
N
distinguishable threshold voltage windows corresponding to the possible N-bit values. As N increases, the threshold voltage windows narrow, and the disturbance of the threshold voltages becomes more difficult to accommodate.
Another problem arises because the memory cells in sectors that are erased frequently age differently from memory cells in sectors that are rarely erased. To compensate for aging or endurance effects, a memory can include circuits that adjust erase, write, or read voltages to compensate for the effects of aging. Different types of compensation can be required for different sectors because the memory cells in different sectors have different histories and have aged differently. Some memories incorporate complex circuitry that monitors the number of erase operations for each sector and operates each sector according to its history. U.S. Pat. Nos. 5,172,338 and 5,163,021, entitled “Multi-State EEPROM Read and Write Circuits and Techniques”, describe Flash memory including circuitry that compensates for differences in aging in different sectors. Such circuitry requires extra overhead, increases circuit complexity, and therefore can increase the cost of a Flash memory.
SUMMARY
In accordance with the invention, a non-volatile memory uses a data management process or arrangement that is not sector-based. This improves storage efficiency because data blocks can be stored without unused storage cells between data blocks. To erase one or more data block from an array, data blocks from the array that are to be saved are read and stored temporarily in a storage device, such as a main memory or a hard disk drive of a computer system connected to the non-volatile memory. The entire memory array is then erased, and the data blocks from the storage device are rewritten in the memory, with the amount of storage originally allocated to the erased data blocks now being available for new data blocks. This data arrangement does not subject any memory cells to a large accumulated write or erase disturbances because all data is read from the array and freshly re-written back after other data blocks in the array are erased. Thus, the accumulated program disturb is limited to only that accumulated from filling the array with data at most once. Additionally, the separate sectors do not have different endurance histories that must be accounted for to extend the life of the memory. A single count of the number of erase operation performed on an array can control voltages used during erase, write, or read operation to extend the usable life of the memory.
One embodiment of the invention is a method for operating a semiconductor memory such as a multi-bit-per-cell Flash memory. The method includes: storing porti

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