Sectored virtual memory management system and translation look-a

Details Sectored virtual memory management system and translation look-a Sectored virtual memory management system and translation look-a

1996-05-30

1999-08-31

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

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Address mapping

711212, 711220, 711144, 711209, G06F 1210

Patent

active

059467169

ABSTRACT:
A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth consumed loading virtual pages into a physical memory. A TLB for this system includes a plurality of TLB entries. Each TLB entry includes a variable physical page number (PPN FIELD) and a variable presence field. Each bit of the presence field indicates whether a corresponding sector is present in physical memory. The TLB entry also includes a page size field, which indicates the size of the corresponding virtual page. This size field also indirectly controls the number of sectors within that page and, thus, the number of presence bits required. As the page size grows the number of bits required to store the physical page number reduces. These unused bits are then consumed by additional presence bits so that all the bits in the TLB entry are used for all page sizes and number of sectors.

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Patterson, David A. and Hennessy, John L., "Computer Architecture a Quantitative Approach", pp. 432-457, 1990.

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