Sectored semiconductor memory device with configurable...

Details Sectored semiconductor memory device with configurable... Sectored semiconductor memory device with configurable...

1998-09-23

2002-06-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S002000, C711S166000

Reexamination Certificate

active

06401164

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a sectored semiconductor memory device with configurable memory sector addresses. Particularly, the invention relates to an electrically erasable and programmable non-volatile memory device, e.g., a Flash EEPROM, comprising individually erasable memory sectors and having configurable memory sector addresses.
BACKGROUND OF THE INVENTION
Flash EEPROMs are non-volatile memory devices which can be programmed and erased electrically. Programming is a selective operation that can involve a single memory location (memory byte or word). On the contrary, erasing is a so-called “bulk” operation, affecting all the memory locations at a time.
Sectored Flash EEPROMs are commercially available which comprise individually erasable memory sectors. In this way, a higher flexibility is achieved because each memory sector can be erased independently from the other memory sectors, so that it is possible not to erase the whole memory locations at a time.
For some particular applications, it is preferable to have memory sectors of different size. By way of example, 4 Megabits (Mbits) word-organized Flash EEPROMs are commercially available wherein the memory space is divided in seven memory sectors of 32 Kilowords (Kwords), one memory sector of 16 Kwords, one memory sector of 8 Kwords and two memory sectors of 4 Kwords. The seven memory sectors of 32 Kwords can for example be used for storing the larger part of a microprocessor code. The memory sector of 16 Kwords, the memory sector of 8 Kwords and the two memory sectors of 4 Kwords form altogether the so-called “boot sector” of 32 Kwords, suitable for example for storing the start-up part code that is rarely subjected to modifications.
It is known that the market demands Flash EEPROMs with both top boot sector configuration and bottom boot sector configuration. In the former, the memory locations of the boot sector correspond to the highest addresses of the memory address space, while in the latter the memory locations of the boot sector correspond to the lowest addresses of the memory address space.
FIGS. 1A and 1B
respectively illustrate the differences between the top and bottom boot sector configurations in the above-mentioned example of a 4 Mbits word-organized Flash EEPROM. Such a memory has a size of 256 Kwords, and 18 address signals allow for individually addressing each memory location. Address signals A
12
-A
17
, that are a subset of the set of external address signals supplied to the memory device, are used for selecting one of the 11 memory sectors; an “X” in the tables of
FIGS. 1A and 1B
conventionally means a “don't care” logic state.
Referring to
FIG. 1A
, wherein the boot sector is located at the top of the address space, the decoding scheme for address signals A
12
-A
17
is the following: if the three most significant address signals A
15
-A
17
are different from “111”, then one of the seven sectors of 32 Kwords is addressed, depending on the particular logic configuration of signals A
15
-A
17
; address signals A
12
-A
14
, together with the remaining subset of twelve least significant external address signals A
0
-A
11
(not shown in the drawing) are used for selecting a particular memory word among the 32 Kwords of the currently selected memory sector. If A
15
=A
16
=A
17
=“1”, then the boot sector is selected. To decide which of the four memory sectors of the boot sector is addressed, address signals A
12
-A
14
are used. If A
14
=“0”, then the 16 Kwords sector is addressed, and A
12
, A
13
, together with A
0
-A
11
, are used to select one among the 16 Kwords. If differently A
14
=“1”, A
13
is considered: if A
13
=“1”, then the 8 Kwords memory sector is addressed, and A
12
, together with A
0
-A
11
, is used to select one among the 8 Kwords. Finally, if A
13
=“0”, either one or the other of the two 4 Kwords memory sectors is addressed depending on A
12
being “1” or “0”; A
0
-A
11
are used to select one among the 4 Kwords of the selected sector.
The situation in the case of a memory device with a boot sector located at the bottom of the address space, shown in
FIG. 1B
, is completely similar, the only difference being that the values of the address signals A
12
-A
17
are the logic complements of those in FIG.
1
A.
Up to now, the request of providing Flash EEPROMs with either a top or a bottom boot sector configuration has imposed the necessity of producing two different kinds of devices, differing in some of the photolithographic masks used in the manufacturing process (e.g., the mask for defining the metal interconnections). This obviously increases the production costs, because two manufacturing lines are necessary, and also the testing scheme of the two kinds of devices is different.
SUMMARY OF THE INVENTION
In view of the state of the art described, it is an object of embodiments of the present invention to provide a sectored memory device with configurable memory sector addresses, thus overcoming the drawback of having to produce and test different devices.
According to aspects of the present invention, such object is achieved by a memory device comprising a plurality of independent memory sectors, external address signal inputs for receiving external address signals for addressing individual memory locations of the memory device, the external address signals comprising external memory sector address signals allowing for individually addressing of each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. The memory device also includes a first and a second alternative internal memory sector address signal paths for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion and a programmable circuit for activating either one or the other of the first and second internal memory sector address signal paths so that a position of each memory sector in a space of values of the external address signals can be changed by activating either one or the other of the first and second internal memory sector address signal paths.
Thanks to the aspects of present invention, only one device can be produced and tested, and the production costs are therefore reduced. The top or bottom configuration of the memory device can be set at the end of the testing of the memory device, by simply programming the programmable means (e.g., a fuse or a non-volatile memory cell).


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