Sector synchronized test method and circuit for memory

Details Sector synchronized test method and circuit for memory Sector synchronized test method and circuit for memory

2005-08-16

2005-08-16

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189040, C324S765010

Reexamination Certificate

active

06930937

ABSTRACT:
A sector synchronized test method and circuit for a memory, applicable for testing several electrically programmable or electrically erasable memory dies. The section synchronize test circuit has a read-write device, a selected switch, and a plurality of test interfaces. While programming or erasing the memory dies simultaneously, the selected switch connects the parallel output terminal, so that the memory dies are connected in parallel. Meanwhile, the read-write device receives a test signal to perform the program or erase operation on the memory dies according to the test signal.

REFERENCES:
patent: 5736850 (1998-04-01), Legal
patent: 5838163 (1998-11-01), Rostoker et al.
patent: 5861660 (1999-01-01), McClure
patent: 2002/0021140 (2002-02-01), Whetsel
patent: 2002/0070748 (2002-06-01), Ernst et al.
patent: 2001-176299 (2001-06-01), None

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