Static information storage and retrieval – Read/write circuit – Erase
Patent
1991-10-28
1993-12-14
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365184, 365182, 257314, 257321, G11C 1300, G11C 1104, G11C 1604
Patent
active
052709809
ABSTRACT:
A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided that applies a first erase voltage to the control gates of selected floating gate memory cells of the array to prevent erasure of the selected floating gate memory cells and a second erase voltage to the control gates of the remaining floating gate memory cells of the array to permit erasure of the remaining floating gate memory cells in a sector erase mode of operation. The decoder is also preferably capable of supplying the second erase voltage to the control gates of each of the floating gate memory cells in a bulk erase mode of operation.
REFERENCES:
patent: 4931997 (1990-06-01), Mitsuishi et al.
patent: 4949309 (1990-08-01), Rao
patent: 4996571 (1991-02-01), Kume et al.
patent: 5034926 (1991-07-01), Taura et al.
patent: 5109361 (1992-04-01), Yim et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
Anagnostopoulos Constantine N.
Caywood John
Pathak Jagdish
Tredwell Timothy J.
Eastman Kodak Company
LaRoche Eugene R.
Nguyen Viet Q.
Woods David M.
LandOfFree
Sector erasable flash EEPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sector erasable flash EEPROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sector erasable flash EEPROM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1711797