Sector-based redundancy architecture

Details Sector-based redundancy architecture Sector-based redundancy architecture

1993-08-26

1994-09-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 371 102, 371 103, G11C 700

Patent

active

053495586

ABSTRACT:
An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors. Addressable storage circuitry (314a,314b) is used for storing sector-based redundancy column addresses, each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column.

REFERENCES:
patent: 5088066 (1992-02-01), Castio
patent: 5270975 (1993-12-01), McAdams
patent: 5278793 (1994-01-01), Yeh

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