Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1999-01-13
2001-11-27
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S322000, C713S400000, C713S401000, C713S500000, C713S501000, C713S601000, C710S015000, C710S018000
Reexamination Certificate
active
06324653
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority of the prior French Patent Application 98-00468 filed Jan. 13, 1998, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuits and more specifically to an integrated circuit comprising a microprocessor and at least one internal peripheral circuit whose operating speed has been improved. A circuit of this type is called a microcontroller.
Microcontrollers are systems generally consisting of a microprocessor or central processing unit and a plurality of internal peripheral circuits required for the operation of the system. These internal peripheral circuits are for example a read-only memory that contains the program to be used by the microcontroller, a programmable memory or a coprocessor.
2. Description of the Prior Art
In the prior art, the speed of operation of the microcontrollers is fixed at the time of their manufacture as a function of the internal peripheral circuits that they contain. This speed is dictated by the internal clock signal of the microcontroller. This signal is fixed and its period is chosen so that all the internal peripheral circuits of the microprocessor can work properly. For example, if the microcontroller has a ROM type memory and an EEPROM type memory respectively having access times t
1
and t
2
, the period of the internal clock signal is taken to be greater than or equal to the greatest of the two access times (in practice t
2
) so that the slowest of these two memories has the necessary time available to carry out the operation controlled by the microprocessor. The duration of an internal clock cycle is therefore permanently greater than or equal to the duration of the read or programming cycle of the slowest memory. More generally, this makes it possible to ensure that, whatever may be the internal peripheral circuit activated by the microprocessor, this circuit will have the time needed to process the instruction coming from the microprocessor.
The speed of operation of the microcontroller is therefore dictated by the slowest internal peripheral circuit of the microcontroller. The overall operation of the microcontroller is thereby then penalized.
In the invention, it is planned to overcome this drawback by matching the operating speed of the microcontroller to the operating time of the internal peripheral circuit activated by the microprocessor.
SUMMARY OF THE INVENTION
Thus, an object of the invention is an integrated circuit comprising a microprocessor driven by an internal clock signal and at least one internal peripheral circuit activated selectively by said microprocessor to perform an operation, wherein said circuit comprises means to match the period of said internal clock signal as a function of the operating time of the activated internal peripheral circuit.
The speed of operation of the integrated circuit is then adapted to the conditions of use of the circuit. Thus, the speed of operation of the integrated circuit is higher when a fast memory is activated than when a slow memory is activated. This matching of the internal clock signal also makes it possible to take precautions against the consequences of possible variations in the manufacturing methods of the elements of the circuit.
To match the period of the internal clock signal, it is planned according to the invention to eliminate the pulses of the internal clock signal during the time taken for the operation performed in the activated internal peripheral circuit. Thus, the means used to match the period of said internal clock signal comprise:
a clock signal generation circuit to generate a primary clock signal that takes the form of a series of pulses dictating a processing speed on the microprocessor, and
a circuit for the conversion of the primary clock signal to eliminate the pulses of said primary clock signal during the time of said operation controlled by the microprocessor in said activated internal peripheral circuit in order to match the period of said internal clock signal to the operating time of the activated internal peripheral circuit, said conversion circuit delivering the internal clock signal.
Thus, the time during which the pulses of the primary clock signal are eliminated depends on the activated internal peripheral circuit.
In order that the microprocessor may benefit from a safety margin between two operations, it is also possible, in the internal peripheral circuits, to provide for additional means for the performance, in parallel with the main operation controlled by the microprocessor, of a second operation whose time is slightly greater than that of the main operation. The pulses of the primary clock signal are then eliminated during the time of this second operation.
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Lisart Mathieu Pierre Gabriel
Wuidart Sylvie
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
Lee Thomas
Nguyen Tanh Q.
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