Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2005-05-24
2005-05-24
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C707S793000
Reexamination Certificate
active
06898661
ABSTRACT:
A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this sequential processing in the memory provides valid data in a bus time plus about half of a cycle time required in repeating reading a conventional memory. Then, the latter half of the cycle time can be used for comparison, as well as generation of the next memory cell address, so that the search can be finished in a bus time multiplied by the number of repetitions of reading the memory cells plus one bus time. As a result, a CAM function can be achieved that allows for more than tens of thousands of entry data items, the number of which is equal to the size of DRAM divided by the number of banks, rather than hundreds or thousands of entry data items as conventional CAM.
REFERENCES:
patent: 5893089 (1999-04-01), Kikinis
patent: 6226710 (2001-05-01), Melchior
patent: 6314506 (2001-11-01), Stanton et al.
patent: 6532468 (2003-03-01), Ishida et al.
Mori Masaya
Sunaga Toshio
Watanabe Shinpei
Canale Anthony J.
International Business Machines - Corporation
Nguyen Hiep T.
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