Sealed three dimensional metal bonded integrated circuits

Details Sealed three dimensional metal bonded integrated circuits Sealed three dimensional metal bonded integrated circuits

2007-05-15

2007-05-15

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S109000, C438S118000, C438S508000, C438S508000, C257S686000, C257S777000, C257SE21503, C257SE21705, C257SE25013

Reexamination Certificate

active

10791492

ABSTRACT:
The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of the volume between the bonded integrated circuits. The material may be the same material as that used for underfilling the volume between the bottom integrated circuit and a substrate.

REFERENCES:
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patent: 6339254 (2002-01-01), Venkateshwaran et al.
patent: 6566745 (2003-05-01), Beyne et al.
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patent: 6777268 (2004-08-01), Jiang
patent: 6820329 (2004-11-01), Fang
patent: 2002/0158318 (2002-10-01), Chen

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