Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reissue Patent
1999-12-23
2002-02-05
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S724000, C257S786000, C257S787000
Reissue Patent
active
RE037539
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same. For example, the present invention is concerned with a DRAM package (a semiconductor device with one or plural DRAM chips mounted thereon will hereinafter be referred to herein as “DRAM package”) comprising plural DRAM (Dynamic Random Access Memory) chips (a semiconductor chip capable of functioning as DRAM will hereinafter be referred to herein as “DRAM chip”), as well as a technique which is particularly useful in producing such DRAM package.
A DRAM chip having as a basic configuration a memory array comprising lattice-like arranged dynamic memory cells as well as a DRAM package having such DRAM chip as a basic configuration are known. In the conventional DRAM package, usually, one DRAM chip is mounted thereon and bonding pads used therein are connected to corresponding leads of a lead frame integral with external terminals.
As to the DRAM package carrying a single DRAM chip thereon, it is described, for example, in U.S. Ser. No. 496,280 filed Mar. 20, 1990.
Recent success towards higher integration density and larger memory capacity of a DRAM chip has been remarkable and correspondingly the chip area has been increasing. At the same time, the DRAM package which carries a DRAM chip thereon also tends to become larger in size. As a result, there has developed a problem that the packaging efficiency of a memory system or the like comprising a DRAM package has not greatly improved.
To cope with the above problem, as shown in
FIGS. 65
to
67
, there have been proposed several methods for mounting on a single package a plurality of sub chips (in the case where one package is composed of plural semiconductor chips, those plural constituent semiconductor chips will each be referred to herein as a “sub chip”). More particularly, in
FIG. 65
, a plurality of sub chips
1
E to
1
I are mounted on the surface of a circuit board
7
A. In
FIG. 66
, first a relatively large sub chip
1
J is mounted on a lead frame
3
, then two relatively small sub chips
1
K and
1
L are mounted as adjacently disposed sub chips on the sub chip
1
J. Corresponding pads of the sub chips
1
J and
1
K,
1
L are connected together through a solder bump
10
. Further, bonding pads of the sub chip
1
J are connected to corresponding external terminals, i.e., outer leads
3
B, through bonding wires
5
. On the other hand, in
FIG. 67
, first a sub chip
1
N is die-bonded onto a circuit board
7
B, and pads provided on the sub chip
1
N are bonded to corresponding metallized portions
11
of the circuit board
7
B through bonding wires
8
. Then, the sub chip
1
N is coated with a molding resin
9
, and after the surface of the coating is flattened, a sub chip
1
M is laminated onto the thus-flattened surface of the coating.
The chip mounting methods illustrated in
FIGS. 66 and 67
are described in Japanese Patent Laid Open Nos. 284951/86 and 283634/87, respectively.
SUMMARY OF THE INVENTION
However, with progress of higher integration density and larger capacity of semiconductor chips, the present inventors found out that the following problems were involved in the foregoing chip mounting methods. In
FIG. 65
, since plural sub chips
1
E-
1
I are mounted on the same plane, the area of the circuit board
7
A increases with an increase in the number of semiconductor chips mounted thereon, and hence the package size also becomes larger. In
FIG. 66
, the lower sub chip
1
J must be larger than the upper sub chips
1
K and
1
L by an amount corresponding to the pad portion required for drawing out the bonding wires
5
. Therefore, it is impossible to constitute a package using the same size of sub chips formed in the same manufacturing process, like a DRAM chip for example. In
FIG. 67
, the heat radiation of the lower sub chip
1
N is obstructed, and restriction is placed on the reduction of the package size because it is necessary to use the circuit board
7
B. In all of these methods, moreover, the manufacturing process is complicated and the product yield is deteriorated in comparison with, for example, the conventional packaging method involving direct wire bonding to a lead frame.
It is the first object of the present invention to provide an effective chip mounting method capable of mounting plural sub chips of the same size without sacrificing the heat radiation characteristic of a package and the product yield.
It is the second object of the present invention to attain a large memory capacity and low power consumption of a DRAM package and simplify the manufacturing process for the same package while suppressing the increase in size of the package.
It is the third object of the present invention to realize a DRAM package having a memory capacity plural times that of a package of about the same size and comprising a single DRAM chip and thereby expand the limit of memory capacity of DRAM chips, etc.
It is the fourth object of the present invention to enhance the packaging efficiency of a memory system or the like having a DRAM package as a basic configuration and reduce the cost thereof.
It is the fifth object of the present invention to provide concrete means for an effective address system and a manufacturing process both suitable for the new chip mounting method and provide several application examples of this chip mounting method.
It is the sixth object of the present invention to provide an effective manufacturing method suitable for the new chip mounting method.
Of numerous improved aspects disclosed herein, a typical one will now be described briefly. A pair of DRAM chips are mounted oppositely to face each other and are provided on both sides of wiring means such as a lead frame which is substantially integrally formed with external terminals, and these DRAM chips and lead frame are connected together by a conventional wire bonding method for example. Plural pairs of such DRAM chips and lead frames thus connected are stacked and corresponding leads of the lead frames are connected in common to provide a laminate. Further, plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip select signal. Additionally, partial DRAM chips capable of normally functioning partially are combined, utilizing this chip mounting method, to constitute a single DRAM package.
According to the above means it is possible to provide an effective chip mounting method capable of mounting plural sub chips of the same size without sacrificing the heat radiation characteristic of the package and the product yield. Besides, it is possible to attain large memory capacity and low power consumption of the DRAM package and simplify the manufacturing process for the package. Moreover, it is possible to realize a DRAM package having a memory capacity plural times that of a package comprising a single DRAM chip and thereby expand the limit of memory capacity of DRAM chips; at the same time it is possible to enhance the packaging efficiency of a memory system having a DRAM package as a basic configuration and reduce the cost thereof. Further, it is possible to utilize partial DRAM chips without waste and enhance a substantial product yield of DRAM chips, etc.
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pate
Anjoh Ichiro
Ishihara Masamichi
Ito Kazuya
Kasama Yasuhiro
Matsuno Youichi
Graybill David E.
Hitachi , Ltd.
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