Sea-of-cells array of transistors

Details Sea-of-cells array of transistors Sea-of-cells array of transistors

2007-04-17

2007-04-17

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10719357

ABSTRACT:
The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

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