Semiconductor memory device having Y-select gate voltage...

Details Semiconductor memory device having Y-select gate voltage... Semiconductor memory device having Y-select gate voltage...

1999-09-23

2001-01-23

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S190000

Reexamination Certificate

active

06178136

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to the Y-select circuits within semiconductor memory devices.
BACKGROUND OF THE INVENTION
Semiconductor memory devices typically have a large number of memory cells arranged into one or more arrays. The memory cells can be accessed by activating a word line which connects a row of memory cells to bit lines, thereby providing access to the row of memory cells. In the event the access is a read operation, output data signals are provided by the memory cells. In the event the access is a write operation (or for some memory devices a program or erase operation), input data signals will be provided on the bit lines. In order to provide as dense a memory device as possible, the memory cells are usually made as small as possible. For many memory cell types, dynamic random access memory (DRAM) cells as just one example, a smaller memory cell size results in a correspondingly smaller output data signal.
Most memory cells include an access transistor that is situated between a bit line and the data-storing portion of the memory cell. As just a few examples, in the case of DRAM cell, an access transistor is situated between a storage capacitor and an associated bit line. In the case of a static RAM (SRAM), one or more access transistors are situated between a latching circuit and one or more bit lines. In the case of a one-transistor (1-T) electrically programmable read-only-memory (EEPROM) cell, the 1-T structure functions both as an access transistor as well as an indicator of a stored data value. Certain access transistor arrangements have result in specialized circuits.
In the case of DRAMs, the access transistor is usually an n-channel metal-oxide-semiconductor (NMOS) transistor that is turned on by the application of a positive gate voltage. In order to prevent the NMOS transistor from introducing a threshold voltage drop between its capacitor and bit line, many DRAMs drive the gates of their access transistors with a “pumped” voltage. The pumped voltage (VPP) is a voltage that is greater than the high supply voltage (VCC) of a DRAM. An example of the utilization of a pumped voltage in a DRAM write, read and refresh operation, will be explained in conjunction with FIG.
1
.
FIG. 1
sets forth a portion of memory cell array
100
including four memory cells (M
00
-M
11
) formed at the intersection of two bit lines (
102
a
and
102
b
) and four word lines (
104
a
-
104
d
). Each memory cell includes an NMOS access transistor N
100
and a storage capacitor C
100
. In writing a logic “1” to memory cell M
00
, bit line
102
a
is driven to the VCC voltage. With bit line
102
a
at the VCC level, word line
104
a
is driven to the VPP voltage. With the VPP level at its gate, transistor N
100
within memory cell M
00
couples a full VCC level to its corresponding storage capacitor C
100
. This provides as great a charging action as is possible. In a read operation that accesses memory cell M
00
, word line
104
a
is driven to the VPP voltage. In this arrangement, in the event memory cell M
00
stores a logic 1 (its capacitor C
100
is charged), a large amount of the charge stored in the storage capacitor C
100
of memory cell M
00
is rapidly placed on bit line
102
a
. The bit line
102
a
can be subsequently driven to the full VCC level by a sense amplifier
108
coupled to the bit line. A refresh operation of cell M
00
is essentially the same as the read operation.
Circuits for generating VPP voltages are now very common in many DRAMs. As a result, such DRAMs will include a low power supply voltage, a high power supply voltage, and the additional, pumped supply voltage.
FIG. 1
also illustrates typical access circuits for a DRAM. In
FIG. 1
, bit lines
102
a
and
102
b
can be considered a bit line pair. This bit line pair (
102
a
and
102
b
) is shown to be connected to a pair of sense nodes (
106
a
and
106
b
) by a pair of pass transistors (N
102
a
and N
102
b
). The pass transistors (N
102
a
and N
102
b
) are commonly activated by a pass signal (PASS). When the PASS signal is active (high), a low impedance path is provided between the pair of bit lines (
102
a
and
102
b
) and the sense nodes (
106
a
and
106
b
). The sense amplifier
108
is disposed between the sense nodes (
106
a
and
106
b
), and serves to amplify voltage differentials between the sense nodes (
106
a
and
106
b
). In
FIG. 1
, in a write operation input data to the bit line pair (
102
a
and
102
b
) is provided from two data nodes (
110
a
and
110
b
). In a read operation, output data from the bit line pair (
102
a
and
102
b
) is provided at the two data nodes (
110
a
and
110
b
).
A signal path between the data nodes (
110
a
and
110
b
) and the sense nodes (
106
a
and
106
b
) is provided by a pair of “Y-select” transistors (N
104
a
and N
104
b
). Y-select transistors derive their name from the fact that they access a particular memory array column (which is disposed in the Y-direction of the array, the rows being disposed in the X direction). As shown in
FIG. 1
, transistors (N
104
a
and N
104
b
) are commonly enabled by a Y-select signal (YSEL).
The conflicting requirements of read operations and write operations have required compromises in the approach to creating the Y-select transistors (N
104
a
and N
104
b
). In addition, the same conflicting requirements can lead to burdensome design changes when optimal read and write operations are sought. For read operations, it is desirable to have a high noise margin. In the event the Y-select transistors and the size of the sense amplifier devices are too large, the logic “0” signal will degrade, and can result in an erroneous data sensing operation. At the same time, in order to minimize the amount of time required between consecutive read operations, it is desirable to limit the voltage swing on the data lines (
110
a
and
110
b
). By doing so, the speed at which the data lines (
110
a
and
110
b
) can be driven from one logic state to an opposite logic state can be increased. The requirements for an optimal read operation (increased noise margin and reduced output data signal swing) can both be served by making the Y-select transistors (N
104
a
and N
104
b
) relatively small devices. Accordingly, for optimal read operation results, the Y-select transistor (N
104
a
and N
104
b
) channel widths should be small.
Optimizing Y-select transistor sizes for read operations can adversely affect write operations, however. In order to make the write operation as fast as possible, input data signals on the data lines (
110
a
and
110
b
) should drive the sense nodes (
106
a
and
106
b
) as rapidly as possible. It is therefore desirable to have the Y-select transistors (N
104
a
and N
104
b
) provide as low a resistance as possible during a write operation. Thus, for optimal write operation results, the Y-select transistor (N
104
a
and N
104
b
) channel widths should be large. This is in contradiction to the optimal transistor sizing for read operations.
The conflicting requirements of read and write operations has resulted in conventional approaches striking a compromise in the sizing of the Y-select transistors (N
104
a
and N
104
b
). Transistor size, and hence write speed, is traded off in order to provide acceptable read functionality. Due to unpredictable process variations, which can affect various portions of the entire data path, it may not always be possible to select the exact Y-select transistor sizes necessary. As a result, an initial manufactured product may provide inadequate performance, or even be nonfunctional because the Y-select transistors are either too large or too small. This requires that at least one subsequent modified design be created with re-sized Y-select transistors. Due to the critical location of Y-select transistors within the very dense memory array layout, such a re-sizing operation can be a tedious and time-consuming task. Thus, each Y-select re-sizing operation introduces a delay in the time t

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