SDRAM memory controller with multiple arbitration points during

Details SDRAM memory controller with multiple arbitration points during SDRAM memory controller with multiple arbitration points during

1995-12-22

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711158, 395729, 395860, G06F 1318

Patent

active

058025812

ABSTRACT:
A computer system having a unified memory architecture (UMA) with a central SDRAM memory can be accessed by multiple devices. Arbitration logic receives and arbitrates among the memory requests. The memory controller indicates when the arbitration logic may issue a grant. The memory controller has two arbitration points during a memory cycle, an early one and a late one. A central processing unit (CPU), or other device, that misses the early arbitration point can still get memory access during the memory cycle by submitting a memory request before the late arbitration point.

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patent: 5708791 (1998-01-01), Davis

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