SDRAM memory controller while in burst four mode supporting sing

Details SDRAM memory controller while in burst four mode supporting sing SDRAM memory controller while in burst four mode supporting sing

1995-12-22

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

395855, G06F 1204

Patent

active

058025979

ABSTRACT:
An SDRAM memory controller that provides both burst four and single data transfers while keeping the SDRAM in burst four mode. A memory controller of data on the data bus during the time that the last 3 data elements is set high for two clock cycles causing the data bus to float during the time that the second and third data elements would have been on the bus. preventing the second and third data elements from being written to memory. During a read, the precharge command causes the bus to float during the time the fourth element would have been on the bus. During a write, the precharge command prevents the fourth data element from being written.

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