Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-12-15
2002-11-26
Kim, Hong (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C326S039000, C713S503000, C713S400000, C716S030000
Reexamination Certificate
active
06487648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous dynamic random access memory (SDRAM), and particularly to an SDRAM controller implemented in a programmable logic device (PLD).
2. Description of the Related Art
The clock rates of the first microprocessors were limited to a range between 1 and 10 Mhz. Typically, even the simplest of instructions, required several clocks to execute. Assuming a main memory cycle time of 250 nanoseconds, approximately 4 million accesses to main memory were needed every second to maintain the first processors at their maximum speed. Asynchronous dynamic random access memory (DRAM) chips, having an access time of 80-100 nanoseconds, met these requirements.
Next generation microprocessors advanced to internal clock speeds in excess of 100 Mhz. However, the DRAM of the time, which had advanced to 60 nanosecond access time, thereby still requiring 10-12 clock cycles to fill a cache line, could not keep pace with those microprocessors. To solve this problem, Fast Page Mode (FPM) DRAMs and EDO (Extended Data Out) DRAMs were developed which provided some performance improvement.
Eventually, improvements in semiconductor processing technology enabled microprocessors to operate beyond 133 Mhz. However, development of a memory device to take full advantage of this speed proved more difficult. Virtually all then available DRAM devices used asynchronous clocking systems, i.e. the clocking signals necessary to perform memory access functions were not synchronized to the associated microprocessor. Specifically, although memories were accessed by signals sent by the microprocessor, the exact time interval between the time a request was sent to a memory and the time a response was received was dependent on the particular internal features of the memory. Thus, system designers had to allow for the “worst case” response time between requests for information and the anticipated time the information would be available. This “worst case” response time necessarily wasted time in handling many memory functions.
After extensive research, a type of memory called synchronous DRAM (SDRAM) was developed to operate with these megafast microprocessors. SDRAM is a generic name for various kinds of DRAM that are synchronized with the optimal clock speed of the microprocessor. In this manner, an SDRAM can increase the number of instructions that the microprocessor can perform in a given time.
Typically, SDRAMs are fabricated as separate integrated circuits from other system components. The SDRAMs, microprocessor, and other components of the system are interconnected via a system bus. An SDRAM controller, which is placed between the system bus and the SDRAM, facilitates communication between the microprocessor and the SDRAM, as well as provides a “window” into the functioning of the SDRAM.
Currently, many of these SDRAM controllers are application specific integrated circuits (ASICs), which provide specific functionality for predetermined SDRAMs. Unfortunately, the extensive engineering necessary to develop and the long lead time associated with the manufacture of these custom devices render ASIC SDRAM controllers an expensive component of the system. This disadvantage is further exacerbated by the continuing fast pace of SDRAM technology development. Thus, by the time an ASIC SDRAM controller is placed in the system and the system is commercially available, new features are introduced on the next generation of SDRAM devices, thereby necessitating another expensive, ASIC development.
Therefore, a need arises for a device to implement an SDRAM controller which reduces the current lead time development of the controller as well as the time to market.
SUMMARY OF THE INVENTION
In accordance with the present invention, a programmable logic device (PLD) implements the SDRAM controller. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. For example, in one embodiment, the number of locations as well as the sequence of memory access in the burst mode are programmable in the PLD.
The state machine, implemented by the configurable logic of the PLD, includes the following steps during a Write operation. If the system issues a WRITE command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Write Wait for Ras-to-Cas Delay state. However, if the system issues a WRITE command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Write Command state in which the controller issues data and a WRITE command to the SDRAM. After the WRITE command is issued, the controller continues to provide data in a Write state until burst end, at which time the controller returns to an Idle state.
The state machine includes the following steps during a Read operation. If the system issues a READ command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Read Wait for Ras-to-Cas Delay state. However, if the system issues a READ command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Read Command state and issues a READ command to the SDRAM. After the Read Command state, the controller automatically enters a Read Command, Wait for Cas Latency state. After the Read Command, Wait for Cas Latency state, the controller reads data in a Read state until burst end, at which time the controller enters an Idle state.
Specific PLDs, such as the Xilinx Virtex field programmable gate arrays (FPGAs), provide features which optimize the design of the SDRAM controller. In accordance with the present invention, dedicated circuits of the PLD eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock. These dedicated circuits include a first delay locked loop (DLL) receiving the system clock and outputting the SDRAM clock and a first feedback signal to the first DLL, and a second DLL receiving the system clock and outputting a second feedback signal to the second DLL. Of importance, the first feedback signal is external to the PLD and the second feedback signal is internal to the PLD.
In one embodiment, a global clock buffer on the PLD drives the system clock to the first and second DLLs. Other global clock buffers on the PLD drive the feedback signals to the DLLs.
Other dedicated circuits that optimize the SDRAM controller include a flip-flop associated with each input and output buffer of the input/output (I/O) blocks in the PLD. The present invention registers the input signals from and output signals to the SDRAMs. The I/O block further includes a programmable delay connected to the D input of the flip-flop registering the input signals to the PLD. The delay in matched to the internal clock distribution delay of the PLD, thereby eliminating pad-to-pad hold time.
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Harms Jeanette S.
Kim Hong
Xilinx , Inc.
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