SDRAM controller

Details SDRAM controller SDRAM controller

2011-03-29

2011-03-29

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S158000, C710S113000, C710S309000

Reexamination Certificate

active

07917706

ABSTRACT:
A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.

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ARM, PrimeCell MultiPort Memory Controller (PL172) Technical Reference Manual, 2002, pp. 16 as found on www.armsemi.com/pdfs/DDI0215D—mpmc—pI172—r2p3—trm.pdf on Mar. 29, 2006.

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