SDRAM clocking test mode

Details SDRAM clocking test mode SDRAM clocking test mode

1997-01-22

1998-05-26

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Testing

36518903, 365191, 365233, G11C 700

Patent

active

057577056

ABSTRACT:
A test circuit provides a test clock signal to a SDRAM of the type having an internal clock input. The test circuit and the SDRAM are housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal, and a test enable terminal adapted to receive a test enable signal. The test circuit includes a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal of the package, and an output coupled to the internal clock input of the SDRAM. The logic circuit couples the clock terminal to the output of the logic circuit in response to the clock enable signal being active and the test enable signal being inactive. The logic circuit derives the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applies the test clock signal to the output of the logic circuit when the test enable signal is active. The test clock signal has a frequency that is greater than the frequencies of the periodic signals.

REFERENCES:
patent: 5386385 (1995-01-01), Stephens, Jr.
patent: 5450364 (1995-09-01), Stephens, Jr. et al.

Affiliated with

Also associated with

Rating

SDRAM clocking test mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SDRAM clocking test mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SDRAM clocking test mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1971054