Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-02-18
2003-10-21
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S314000, C710S315000, C714S002000, C714S004110
Reexamination Certificate
active
06636921
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the addressing of multiple disk drives within computing systems and more particularly to a repeater circuit for enabling and addressing terminated bus segments.
2. Description of the Related Art
With the ever increasing amount of data being processed by today's computing systems, a mass storage subsystem is often desired for transferring large amounts of data to and from the computing system. Such a mass storage subsystem is commonly found in a local area network (LAN), wherein information and files stored in the mass storage subsystem are distributed, through one or more servers, to local work stations having limited or no mass storage capabilities.
The servers typically communicate with the mass storage subsystem through what is known as a Small Computer System Interface (SCSI) bus. To maximize the performance of the SCSI bus, the SCSI bus should not exceed a predetermined length. This predetermined length can be exceeded when a server, located in one box or unit, is connected through a SCSI cable to the mass storage subsystem, such as a disk drive array or a CD-ROM drive located in another box or unit. To prevent performance degradation, designers have implemented what is known as repeater circuits which are used to couple short, terminated SCSI bus segments. The repeater circuit includes two ports with each port connected to a different terminated SCSI bus segment. The repeater circuit provides a buffer between the terminated bus segments in order to achieve a high performance SCSI bus that exceeds the predetermined length.
Many disk storage subsystems typically use what is referred to as a narrow SCSI bus, which allows the addressing of up to eight SCSI devices and providing eight bit data transfers. In a typical narrow SCSI bus configuration, a SCSI bus controller, otherwise known as an initiator, occupies one address bit or SCSI ID bit; the remaining SCSI ID bits are occupied by up to seven disk drives, which are referred to as targets. The narrow SCSI bus should be contrasted to a higher performance SCSI bus, commonly referred to as a wide SCSI bus, which allows the addressing of up to sixteen SCSI devices and provides sixteen bit data transfers. In a typical wide SCSI bus configuration, the initiator will occupy one SCSI ID, and the remaining SCSI IDs will be occupied by up to fifteen targets. A typical solution for allowing a server using a wide SCSI bus to be fully compatible with a storage subsystem using a narrow SCSI bus has been for the server to downgrade its own performance to match that of the narrow SCSI bus, thereby sacrificing the performance advantage offered by the wide SCSI bus.
SUMMARY OF THE INVENTION
Briefly, the present invention relates to a SCSI bus repeater circuit that isolates devices on a terminated SCSI bus segment by buffering all SCSI bus signals. The physical configuration of a storage subsystem may contain many terminated SCSI bus segments, some of which may be narrow SCSI buses. The present invention relates to a repeater circuit that provides SCSI address translation so two repeater circuits can couple two narrow SCSI buses to one wide SCSI bus with the two narrow SCSI buses then appearing as a single logical wide SCSI bus. Thus, a SCSI bus server coupled to the wide SCSI bus can maintain compatibility with a narrow SCSI bus storage subsystem without the SCSI bus server sacrificing the performance of a wide SCSI bus. Thus, the repeater circuit of the present invention provides logical mapping for terminated bus segments.
The present invention also relates to a repeater circuit which can be utilized in a fault tolerant storage system. In such a system, the repeater circuit is coupled to a first terminated SCSI bus connected to a server and a second terminated SCSI bus connected to target devices. In the preferred embodiment, the repeater circuit has a reset detection circuit that detects inband signaling by an inactive secondary server coupled to the first bus. This in-band signaling indicates that an active primary server has failed and the secondary server has detected this failure. The repeater circuit provides a switch signal, indicative of this condition, to an embedded controller of the storage subsystem. The embedded controller then enables and disables repeater circuits of the storage subsystem accordingly in order to provide a fault tolerant, mass storage subsystem.Thus,
Thus, the repeater circuit of the present invention provides logical mapping for terminated bus segments. Furthermore, the repeater circuit allows sections of terminated SCSI bus segments of a network, coupled to one or more SCSI devices, to be switched in and out of the network dependent on the status of the servers of the network.
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Galloway William C.
Scholhamer George J.
Dharia Rupal
Hewlett-Packard Development Company LP.
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