Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2000-02-18
2003-04-08
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S600000
Reexamination Certificate
active
06546497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of and apparatus for a SCSI controller or repeater. More particularly, the present invention relates to a controller or initiator that stretches the SCSI REQ and ACK clock signals.
2. Description of the Related Art
As long as there have been computers, users have attached peripheral hardware devices to them. Some of the typical hardware interfaces include Integrated Drive Electronics (IDE) and Enhanced IDE (EIDE) buses. One of the more popular and enduring interfaces is the small computer system interface (SCSI) bus. While an IDE bus is restricted to two disk drives and an EIDE bus is restricted to four devices, including hard disks and CD-ROM drives, the SCSI bus is able to support up to fifteen devices such as disk drives, CD-ROM drives, optical drives, printers, and communication devices. One of the attractions of the SCSI bus is its ability to easily adapt to new types of devices by using a standard set of commands, or the SCSI-3 command set.
The SCSI protocol specifies that communication between an initiator, or device that issues SCSI commands, and a target, a device that executes SCSI commands, takes place in phases: BUS_FREE, ARBITRATION, SELECTION, RE-SELECTION, COMMAND, DATA, MESSAGE_IN, MESSAGE_OUT and STATUS. The first four phases, BUS_FREE, ARBITRATION, SELECTION, and RE-SELECTION, are known collectively as the ADDRESS phases and are used to setup a connection between an initiator and a target device.
The BUS_FREE phase is the initial state and, during the BUS_FREE phase, any SCSI device on a particular SCSI bus can attempt to take control of the bus. Often two or more devices request control at the same time (or within the period of a “bus settle delay” typically 400 ns). Which device gains control is determined in the ARBITRATION phase. After the ARBITRATION phase, the SELECTION phase is performed where the initiator selected in the ARBITRATION phase signals a specific target device that a service is requested. The RE-SELECTION phase is required when an interrupted connection needs to be reestablished.
The final phases, COMMAND, DATA, MESSAGE_IN, MESSAGE_OUT and STATUS, are known collectively as the DATA phases. During the DATA phases, the target device receives commands from the initiator, the two exchange data, and, if necessary, messages and status information are communicated.
If a data transfer is asynchronous, the initiator and the target participate in a handshaking scheme to insure the reliability of the communication. Typically, every data element sent is accompanied by a clock. The target uses the REQ# signal to initiate transfers; the initiator uses an ACK# signal to complete transfers. In the case DATA_IN, or a target sending data to a initiator, the target asserts the REQ# signal to indicate that a byte or word is available and the initiator asserts the ACK# signal to indicate that the byte or word has been received. In the case of DATA_OUT, or a target receiving data from the initiator, the target asserts REQ#, to which the initiator responds by placing data on the bus and asserting ACK#. The target then de-asserts REQ# to acknowledge receipt and the initiator asserts ACK# in response. The handshaking requirements of the SCSI protocol add a large overhead to asynchronous data transfers.
A synchronous data transfer, on the other hand, does not require this element-by-element protocol. During synchronous data transfer, a target does not wait for an individual acknowledgement of each transfer, but rather, employs an “offset value” and transmits that number of REQ#s before requiring an ACK#. The offset is a limit on the number of unacknowledged REQ#s that are allowed before the target must pause and wait for an acknowledgement from the initiator. The data in asynchronous transactions is clocked by the sender's REQ# or ACK# line.
To maximize performance, a SCSI bus should not exceed a predetermined length. For example, the predetermined length can be exceeded when a server, located in one box or unit, is connected through a SCSI bus to a mass storage subsystem, such as a disk drive array or a CD-ROM drive located in another box or unit. To prevent performance degradation, designers have implemented what is known as repeater circuits. Repeater circuits are used to couple short, terminated SCSI bus segments. The repeater circuit includes two ports with each port connected to a different terminated SCSI bus segment.
The repeater circuit provides a buffer between the terminated bus segments in order to achieve a high performance SCSI bus that exceeds the predetermined length. To a SCSI controller, the terminated bus segments appear as a single SCSI bus.
SUMMARY OF THE INVENTION
The present invention relates to a SCSI repeater, initiator, or controller that “stretches” the SCSI REQ# or ACK# clock signals when the SCSI data bus has been idle for a predetermined period of time. When a SCSI bus has been idle for a certain period of time, the REQ# and ACK# signal lines can become “precharged” with a DC load. According to the invention, this load is first “discharged” by asserting the first REQ# or ACK# signal for a longer than normal period of time.
For example, after one microsecond of inactivity, the first asserted pulse of the REQ# or ACK# signals is asserted low for
100
ns, irrespective of what the SCSI data rate is on a particular transaction.
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Elliott Robert C.
Galloway William C.
Akin Gump Strauss Hauer & Feld & LLP
Heckler Thomas M.
Hewlett--Packard Development Company, L.P.
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