Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-06-30
2002-11-05
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000
Reexamination Certificate
active
06477601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data transfers over a SCSI bus, and in particular to detecting and managing signals associated with the SCSI Bus Free phase on a SCSI bus.
2. Description of Related Art
Prior single chip parallel SCSI host adapters have included a plurality of modules and an on-chip processor that controlled operation of the modules. For example, see U.S. Pat. No. 5,659,690, entitled “Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor,” issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference.
A typical parallel SCSI host adapter
100
included a SCSI module
130
(FIG.
1
), a sequencer
120
, a data FIFO memory circuit
160
, a memory
140
, and a host interface module
110
that were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit
100
both by a host microprocessor
170
through a host adapter driver
165
and by sequencer
120
. The combination of host adapter driver
165
, sequencer
120
, and SCSI module
130
were used for controlling both synchronous and asynchronous transfers over SCSI bus
150
.
One of the functions performed by host adapter integrated circuit
100
was detection of both expected and unexpected Bus Free phases on SCSI bus
100
. A Bus Free phase is the interval when no SCSI device is connected to SCSI bus
150
. The Bus Free phase is expected by host adapter
100
in specific situations, e.g., after assertion of acknowledge signal ACK to a disconnect completion, after a Bus Device Reset message, or after an Abort message. An unexpected Bus Free phase is one that occurs as a result of an accident any time during a SCSI information transfer.
The Bus Free phase detection technique used in host adapter
100
was a simple level detector. The management of the Bus Free phase required an appreciable amount of sequencer firmware. Moreover, since the Bus Free phase management occurred in time critical sequences, execution of this appreciable amount of sequencer firmware affected the performance of host adapter
100
.
For example, after every successful selection of a target and again after reselection by a target, sequencer
120
cleared the Bus Free phase status associated with a previous selection or reselection, and re-enabled a Bus Free phase interrupt. This required execution of three sequencer instructions in each instance: a first instruction to clear the Bus Free phase status; a second instruction to enable the Bus Free phase interrupt; and a third instruction to check the SCSI bus phase status to assure that a Bus Free phase did not occur immediately prior to enabling the interrupt.
The three instructions could not be executed before a completed selection or reselection because at that time SCSI bus
150
typically was in the Bus Free phase. Therefore, execution of the instructions would result in a status of Bus Free phase and generation of the associated interrupt. Since the three instructions had to be executed after the completed selection or reselection, the instructions were typically executed while a target was waiting for assertion of acknowledge signal ACK.
The Bus Free phase interrupt was enabled when the Bus Free phase was not expected. In the event of an unexpected Bus Free phase on SCSI bus
150
, which meant a catastrophic drop-off of a target from SCSI bus
150
, the Bus Free phase interrupt was generated which halted sequencer
120
and prevented further execution of a sequencer control block (SCB). In addition, an interrupt was asserted to host adapter driver
165
notifying driver
165
of the catastrophe.
In response to the interrupt, host adapter driver
165
determined the cause of the interrupt by scanning status bits in host adapter
100
. To prevent another redundant interrupt due to the Bus Free condition, host adapter driver
165
disabled the Bus Free phase interrupt, and cleared the status of Bus Free phase.
At points during the SCSI bus phase sequence when sequencer
120
expected a Bus Free phase, sequencer
120
disabled the Bus Free phase interrupt just before the Bus Free phase was expected. This prevented generation of the interrupt to host adapter driver
165
when the Bus Free phase occurred. The Bus Free phase always occurred after certain messages and so sequencer
120
disabled the Bus Free phase interrupt just prior to asserting acknowledge signal ACK in response to one of the messages.
However, the Bus Free phase status detection was always enabled. The Bus Free phase status was latched for sequencer
120
because the Bus Free phase could be very short, and could be missed by sequencer
120
. Sequencer
120
always waited for the Bus Free phase status when it was expected, because some targets asserted another request signal REQ instead of going to the Bus Free phase when a parity error occurred. Sequence
120
has to be able to detect this situation, which in turn required waiting for the Bus Free phase status.
SUMMARY OF THE INVENTION
According to the principles of this invention, a Bus Free management circuit in a SCSI module of a parallel SCSI host adapter integrated circuit reduces the number of sequencer firmware instructions that must be executed prior to responding to an assertion of a request signal REQ on a SCSI bus following a selection complete or a reselection complete. Consequently, the parallel SCSI host adapter integrated circuit asserts acknowledge signal ACK more quickly than in the prior art host adapter integrated circuit that required execution of at least three sequencer firmware instructions to manage the Bus Free phase detection prior to assertion of acknowledge signal ACK.
The parallel SCSI host adapter integrated circuit of this invention includes a Bus Free management circuit having a plurality of input lines coupled to SCSI bus control terminals of the parallel SCSI host adapter integrated circuit; a Bus Free phase interrupt disable line; a clear line; a Bus Free phase status line; and a Bus Free phase interrupt line. The Bus Free management circuit automatically generates an active signal on the Bus Free phase status line following receipt of (i) one of a selection complete signal and a reselection complete signal on the plurality of input lines; and (ii) a Bus Free phase signal on the plurality of input lines.
The parallel SCSI host adapter integrated circuit also includes a circuit coupled to the clear line, to the Bus Free phase status line, and to the Bus Free phase interrupt disable line. The circuit generates an active signal on the Bus Free phase interrupt disable line when a Bus Free phase is expected. The circuit also generates an active signal on the clear line after determining that an active signal is on the Bus Free phase status line.
In one embodiment, the circuit is an on-chip sequencer. In another embodiment, the circuit includes a register that is connected to the clear line. When the register is set either by the sequencer or by a host adapter driver, the active signal is driven on the clear line. The circuit also includes hardware that detects the SCSI bus phase and automatically generates, without any processor intervention, the active signal on the Bus Free phase interrupt disable line when a Bus Free phase is expected.
In one embodiment, the Bus Free management circuit further includes an enable circuit coupled to the plurality of input lines and to the Bus Free phase interrupt disable line. The enable circuit includes an enable line and an output line. The Bus Free management circuit also includes a status generation circuit connected to the enable line and to the clear line, and having an output terminal connected to the Bus Free phase status line. The Bus Free management circuit further includes an interrupt generation circuit connected to the enable line, to the clear line, and to the output line, and having an output terminal connected to the Bus Free phase interrupt line.
A method of this invention first enables automatic hardware generation of a SCSI Bus F
Adaptec, Inc.
Forrest Gunnison
Gunnison McKay & Hodgson, L.L.P.
Vo Tim
Wong Peter
LandOfFree
SCSI bus free phase management structure and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SCSI bus free phase management structure and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SCSI bus free phase management structure and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2993699