Scripted, hierarchical template-based IC physical layout system

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10863122

ABSTRACT:
A computer-aided design tool for automatically generating a layout for an electronic device to be formed by a set of objects implemented within an integrated circuit, receives input from a user defining a device template specifying shapes, dimensions and relative positions within the layout of the objects forming the device. Some of the object dimensions and/or relative positions are specified as functions of values of input parameters to be supplied by the user. When the user supplies the input parameters, the CAD tool evaluates the functions to determine the object dimensions and/or positions that are functions of the input parameters and then generates a layout for the electronic device wherein object shapes, dimensions and relative positions are as specified in the device template and consistent with the function evaluations. The device template may also include instructions for modifying the layout, for example, indicating that copies of an object are to form an array in the layout, that copies of one object are to fill another object, that an object is to be added to the layout having a shape that is a Boolean function of other objects, and that objects are to be added to or removed from the layout.

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patent: 2004/0054659 (2004-03-01), McIntyre

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