Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-02-09
2002-08-27
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
Reexamination Certificate
active
06441465
ABSTRACT:
FIELD OF INVENTION
The invention relates to a scribe line structure of a semiconductor wafer, and in particular, to a scribe line structure with the capability of relieving internal stress and arresting cracks induced during scribe line fabrication for preventing from damages thereof.
BACKGROUND OF INVENTION
Referring to
FIG. 1A
, in a semiconductor wafer
10
, a plurality of substantially parallel horizontal scribe lines
11
and a plurality of substantially vertical scribe lines
11
are always formed over a substrate
14
of the wafer
10
for separating a plurality of chips
13
from each other. In general, the scribe lines are composed of a multi-layer structure without pattern about 100 &mgr;m in width depending on the dimension of chips manufactured in wafer. After being manufactured, a wafer is divided into a plurality of dies by sawing the wafer along the scribe lines thereof. In addition, to prevent cracks induced during wafer sawing operation from propagating into chips, each of a plurality of chips is usually surrounded by a corresponding blank space about 3~10 &mgr;m in width, namely seal ring. That is, as shown in
FIG. 1A
, a corresponding seal ring
12
is usually formed between a chip
13
and a scribe line
11
adjacent to the chip
13
. Nevertheless, during wafer manufacture, some possible damages are introduced into the scribe lines, and further attack the seal rings and chips adjacent to the damaged scribe lines, e.g., peeling, delamination and dielectric fracture. The cause of possible damages of the scribe lines induced during wafer manufacture will be explained as follows.
As mentioned above, a scribe line is composed of a multi-layer structure simply. Moreover, the multi-layer structure generally includes a plurality of conductive layers and insulating layers, and the plurality of conductive and insulating layers are formed over areas of the scribe lines while the conductive and insulating layers are being formed for fabricating the chips. It is noted that profile of each scribe line is like a wide string, i.e., each scribe line has two elongated sides. Consequently, one layer, deposited over the areas of the scribe lines to provide the multi-layer structure, will generate more or less shrinkage along two elongated sides of each scribe line at post deposition cool down step thereof. A large dimension of shrinkage of a layer in the multi-layer structure is significant when the layer is composed of a metal material, especially for metal material with high thermal extension coefficient, such as aluminum. Significant shrinkage of a layer in the multi-layer structure will introduce high level of internal stress into the scribe lines. Thereafter, the scribe lines thereof will suffer from damages induced by high level of internal stress, such as peeling, delamination and dielectric fracture. The damages of the scribe lines mentioned above are usually observed when the multi-layer structure includes an intermetal dielectric layer which is composed of an upper SiO
2
layer, an SOG (spin-on glass) layer, and a lower SiO
2
layer. Nevertheless, the intermetal dielectric layer is usually employed in IC manufacture.
As shown in
FIG. 1B
, the multi-layer structure of the scribe line
11
includes a metal layer
111
and an intermetal dielectric layer
112
composed of a SiO
2
layer
1121
, an SOG layer
1122
, and a SiO
2
layer
1123
. The metal layer
111
and the intermetal dielectric layer
112
are formed over the areas of the scribe lines
11
while they are being formed in a metallization process of the chips
13
. The metal layer
111
is formed after the formation of the intermetal dielectric layer
112
. Thus, high level of inter-layer stress induced by shrinkage of the metal layer
111
between the metal layer
111
and the intermetal dielectric layer is difficult to coordinate. To coordinate the high level of inter-layer stress, delamination
113
of the metal layer
111
will occur, and even induce peeling
114
of the scribe lines
11
, as illustrated in FIG.
1
B. Moreover, high internal stress of brittle dielectric layers also induces fracture thereof Especially for the intermetal dielectric layer
112
, due to poor adhesion between the SiO
2
layer
1221
and the SOG layer
1223
, dielectric fracture
115
easily initiates at the SiO
2
/SOG interface nearing the edge of the scribe lines, as illustrated in FIG.
1
B.
The following prior art references relate to the improvement technology for scribe lines of a wafer.
1. U.S. Pat. No. 5,686,171
2. U.S. Pat. No. 5,414,297
3. U.S. Pat. No. 5,300,816
4. U.S. Pat. No. 5,237,199
5. U.S. Pat. No. 5,136,354
However, the prior arts only focus on the improvement of step coverage or interlayer adhesion of scribe lines of a wafer. The damages of scribe lines induced by high internal stress are not solved in the prior arts.
Accordingly, an objective of the invention is to provide a scribe line structure for preventing from possible damages induced during scribe line manufacture.
SUMMARY OF INVENTION
An objective of the invention is provided a scribe line structure for preventing from possible damages induced during scribe line manufacture, such as peeling, delamination, and dielectric fracture.
According to the invention, in a semiconductor wafer with a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines separating a plurality of chips from each other, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure includes a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure.
The cavities of the scribe line structure are capable of relieving internal stress of scribe lines and arresting possible cracks induced during scribe line manufacture. Thereby, peeling and delamination of the scribe lines during scribe line manufacture can be prevented.
REFERENCES:
patent: 5300816 (1994-04-01), Lee et al.
patent: 5414297 (1995-05-01), Morita et al.
patent: 6025639 (2000-02-01), Mitwalsky et al.
patent: 4-116848 (1992-04-01), None
Feng Min-Shinn
Lin Chi-Fa
Tseng Wei-Tsu
Thomas Tom
Tran Thien F
Winbond Electronics Corp.
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