Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Patent
1995-12-05
1998-07-28
Dutton, Brian
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
324765, H01L 2166, G01R 3126
Patent
active
057862311
ABSTRACT:
A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.
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Devine Roderick A. B.
Fleetwood Daniel M.
Schwank James R.
Shaneyfelt Marty R.
Vanheusden Karel J. R.
Dutton Brian
Hohimer John P.
Sandia Corporation
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