Scrambling method to reduce wordline coupling noise

Details Scrambling method to reduce wordline coupling noise Scrambling method to reduce wordline coupling noise

2007-07-17

2007-07-17

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257SE27108

Reexamination Certificate

active

10968798

ABSTRACT:
A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

REFERENCES:
patent: 5602772 (1997-02-01), Nakano et al.
patent: 5732010 (1998-03-01), Takashima et al.
patent: 6873537 (2005-03-01), Kang
patent: 2003/0072172 (2003-04-01), Somasekhar et al.
patent: 2004/0062069 (2004-04-01), Keeth

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