Scrambling and unscrambling circuit

Details Scrambling and unscrambling circuit Scrambling and unscrambling circuit

1991-03-26

1993-03-02

Buczinski, Stephen C.

Cryptography

Key management

Having particular key generator

380 17, H04N 7167

Patent

active

051916096

ABSTRACT:
There is disclosed a circuit for scrambling an input signal, which has a pseudo-random address generator to detect a synchronizing signal from the input signal and to generate therefrom pseudo-random address and sequential address. The inventive circuit has memories, the input signal being written thereon according to the pseudo-random address from the pseudo-random address generator in a write mode, and the input signal being read out therefrom according to the sequential address from the pseudo-random address generator in a read mode.

REFERENCES:
patent: 4424532 (1984-01-01), Den Toonder et al.
patent: 4731837 (1988-03-01), Gautier
patent: 4910772 (1990-03-01), Matias et al.

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