Scramble detecting circuit in a satellite broadcasting receiver

Details Scramble detecting circuit in a satellite broadcasting receiver Scramble detecting circuit in a satellite broadcasting receiver

1993-04-26

1995-02-21

Gregory, Bernarr E.

Cryptography

Key management

Having particular key generator

380 9, 380 19, 380 49, 380 59, H04L 900

Patent

active

053923529

ABSTRACT:
In a satellite broadcasting receiver for receiving and decoding pulse code modulation (PCM) audio frame data having a plurality of channels, the logical state of charged flags (FD) included in the data of each channel is detected and the charged flags detected at a channel-related period are stored. Then the charged flags of a previous frame are simultaneously gated at the start time of a frame. A plurality of pulses clocking individual frame periods are counted and a multiframe signal spanning a given period is generated. In this case, the logical values of the charged flags gated at multiframe periods are accumulated, and an audio mute signal is generated when charged flags exceeding a given number are detected during a multiframe signal period.

REFERENCES:
patent: 4672440 (1987-06-01), Trahan
patent: 5122912 (1992-06-01), Kanota et al.

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