SCR-ESD structures with shallow trench isolation

Details SCR-ESD structures with shallow trench isolation SCR-ESD structures with shallow trench isolation

2002-07-05

2004-04-13

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S356000, C257S360000, C257S173000, C438S322000, C438S336000

Reexamination Certificate

active

06720622

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to a structure and process for a semiconductor device which provides improved ESD protection for internal active semiconductor devices and more particularly to a semiconductor SCR like device which when used with shallow trench isolation, provides improved parasitic bipolar characteristics resulting in improved ESD protection performance.
(2) Description of Prior Art
The discharge of electrostatic energy from the human body or other sources known as electrostatic discharge (ESD) into the input or output pads of integrated circuit semiconductor devices has shown to cause catastrophic failures in these same circuits. This is becoming more important as modem metal oxide semiconductor (MOS) circuit technology is scaled down in size and increased in device and circuit density. Prevention of damage from ESD events is provided by protection devices or circuits on the input or output pads of the active logic circuits which shunt the ESD energy to a second voltage source, typically ground, thereby bypassing the active circuits protecting them from damage. Various devices such as silicon controlled rectifiers (SCR) have been utilized to essentially shunt the high ESD energy and therefore the ESD stress away from the active circuits.
Isolation is required between these ESD protection devices and the active circuit devices, as well as between the active devices themselves. Originally areas of local thick oxide, often called LOCOS or field oxide, have been used to provide this isolation. While having good isolation properties, this isolation method uses more surface area, or “real estate”, than an alternative isolation method using shallow, relatively narrow trenches filled with a dielectric, typically silicon oxide (SiO
2
), called shallow trench isolation (STI).
While providing good isolation properties, the STI structure has limiting effects on the current triggering and capacity of the SCR ESD protection devices. During STI formation, the STI region is exposed to the etching process, leading to non-plan STI edges where the silicon region extends above the isolation edge. The non-planer STI edge is called “STI pull-down”. The impact of STI pull-down, and the interaction with the silicide process typically used in current contact technology, as well as junction depth reduction of the diode elements bounded by the STI devices, all degrade ESD protection capabilities by reducing the parasitic bipolar current gain, beta, (B). This increases the holding voltage and trigger current of the lateral SCR, reduces lateral heat transfer capability, and possibly limits the type of ESD networks implemented Among other things, this can result in device failure before the SCR is fully on, or a high on-resistance for the SCR reducing the ESD failure threshold.
FIG. 1A
is a simplified cross section of a typical prior art SCR ESD protection device Shown is a P substrate
8
, with an N-well
10
and which contains contact regions N+
16
and P+
18
. The N-well
10
contact regions are isolated and bounded by the shallow trench isolation (STI) structures
12
A,
12
B and
12
C. The N-well
10
is also bounded by STI elements
12
A and
12
C. The P substrate
8
also contains N+ contact
20
bounded by STI elements
12
C and
12
D, and P+ contact
22
bounded by STI structures
12
D and
12
E. Also depicted in
FIG. 1A
are parasitic vertical PNP bipolar transistor T
1
and lateral NPN bipolar transistor T
2
with parasitic resistors R
1
and R
2
. The P+ contact
18
is the anode end of the device and is connected to the active circuit input or output pad
4
as well as to the N-well N+ contact
16
by conductor
24
A.
The junction between the P+ contact region
18
and the N-well
10
is the first junction of the SCR, and the P+ contact region
18
forms the SCR device anode. The N-well
10
and the P substrate
8
form the second junction. The third device junction is formed by the P substrate
8
and substrate N+ contact
20
, which also is the cathode terminal of the device. N+ contact
20
is connected to a second voltage source, typically ground, and also to substrate P+ contact
22
by conductor element
24
B.
FIG. 1B
shows the horizontal topography of the prior art device showing the N-well
10
with associated N+ contact
16
, P+ contact
18
, and related STI structures
12
A,
12
B, and
12
C represented by the dashed lines. Also represented in
FIG. 1B
are the substrate N+ contact
20
and P+ contact
22
as well as the STI
12
D and
12
E. The contact elements often use a silicide, or salicide, to improve the silicon to metal contact conductivity. The salicides are typically formed from refractory metals such as titanium (Ti), tungsten (W), tantalum (Ta), or molybdenum (Mo). The typical process is to provide a barrier such as SiO
2
to prevent salicide formation in unwanted areas, deposit the metal followed by a heat process, to form the salicide, and then remove the metal from the unwanted or non-contact areas.
FIG. 1C
represents the electrical schematic of the prior art device showing the parasitic vertical bipolar PNP transistor T
1
and parasitic lateral NPN bipolar transistor T
2
as well as the resistors R
1
and R
2
. A positive ESD voltage event will cause the T
1
base-collector junction to go into avalanche conduction, turning on T
2
and providing the regenerative conduction action shunting the ESD current to the second voltage source, typically ground. A negative ESD voltage pulse will forward bias the base-collector junction of T
1
, which is formed by the N-well
10
and P-substrate
8
junction, again shunting the current to the second voltage source.
However, for positive ESD events as indicated above, the STI isolation structures inhibit lateral current conduction near the surface, lower the parasitic bipolar semiconductor current gain, and can interfere with device thermal characteristics.
FIG. 2
represents another prior art protection device, a low voltage trigger SCR (LVTSCR). There is no STI between the N-well N+ contact
16
and SCR P+ anode
18
, and the STI structure
12
C formerly straddling the N-well
10
and Substrate
8
boundary has been shifted to the left and a N+ region
28
has been added straddling the lateral boundary. A FET gate
26
has been inserted bete the N+ region
28
and the N+ region
20
which essentially become the drain and source of a NFET respectively. The NFET source region
20
also functions as the SCR cathode. The prior art LVTSCR device operational trigger voltage is reduced by the NFET device breakdown voltage. The remaining STI elements still reduce the desirable ESD protection characteristics as previously discussed.
The invention in various embodiments allows the reduced use of STI elements while improving ESD protection by the use of an oxide layer, often called resistor protection oxide, for a silicide block
The following patents describe ESD protection devices.
U.S. Pat. No. 6,172,403 (Chen) shows an ESD circuit with a process involving AA, isolation areas, and silicide.
U.S. Pat. No. 5,012,317 (Rountie=) shows a conventional SCR-ESD circuit protection device with parasitic bipolar transistors.
U.S. Pat. No. 5,629,544 goldman et al.), U.S. Pat. No. 6, 236,087 (Daly et al.), U.S. Pat. No. 5,903,424, (Taillliet and U.S. Pat. No. 5,530,612 (Maloney) are related ESD patents.
The following technical reports discuss ESD protection circuits and STI bound ESD protection networks.
“Basic ESD and I/O Designed” by S. Dabral et al., 1998 pps 38, 57, 62, and 247.
“Designing Power Supply Clamps for Electrostatic Discharge Protection of integrated Circuits” by T. J. Maloney, Microelectronics Reliability 38 (1998) pp. 1691-1703.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide a novel, effective structure and manufacturable method for protecting integrated circuits, in particular field effect transis

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