SCR devices in silicon-on-insulator CMOS process for on-chip...

Details SCR devices in silicon-on-insulator CMOS process for on-chip... SCR devices in silicon-on-insulator CMOS process for on-chip...

2002-02-05

2004-06-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S338000, C257S347000, C257S350000, C257S355000, C257S356000, C257S368000, C257S369000, C257S371000

Reexamination Certificate

active

06750515

ABSTRACT:

DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a semiconductor device and, more particularly, to an electrostatic discharge protection circuit incorporating a silicon controlled rectifier in a silicon-on-insulator semiconductor device.
2. Background of the Invention
Recent advances in integrated circuits have included further development of a silicon-on-insulator (SOI) technology. An SOI technology uses an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. There are two types of SOI processes, fully-depleted and partially-depleted.
In an SOI complementary metal-oxide semiconductor (CMOS) technology, an independent and isolated n-type metal-oxide semiconductor (NMOS) transistor may be provided next to a p-type MOS (PMOS) transistor, and vice versa, because the NMOS and PMOS transistors are electrically isolated from each other and from the underlying silicon substrate. The main advantage of the SOI CMOS technology includes high immunity to latch-up, low junction capacitance, and low junction leakage current. The latch-up problems can be avoided because the source and drain regions of the transistors are surrounded by an insulator. In addition, an absence of diode junctions around the source and drain regions further reduces leakage current and junction capacitances. However, the SOI CMOS technology is still susceptible to an electrostatic discharge (ESD) event due to poor thermal conductivity of the insulator, e.g., buried oxide, and the floating body effect from active devices being formed over the insulator instead of a semiconductor substrate.
An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to an integrated circuit (IC). The large current may be built-up from a variety of sources, such as the human body. To protect ICs from an ESD event, many schemes have been implemented, including use of a silicon controlled rectifier (SCR). A feature of an SCR is its voltage-holding ability, at approximately 1 volt, in a non-epitaxial bulk CMOS process. In addition, an SCR can sustain high current and hold the voltage across the SCR at a low level, and may be implemented to bypass high current discharges associated with an ESD event.
A conventional SCR device has a switching voltage of more than 30 volts in sub-micron CMOS processes, and therefore is not suitable to protect gate oxides in a sub-micron CMOS technology.
FIG. 1
is a reproduction of FIG. 3 of U.S. Pat. No. 5,012,317 to Rountre, entitled “Electrostatic Discharge Protection Circuit.” Rountre describes a lateral SCR structure made up of a P+ type region
48
, an N-type well
46
, a P-type layer
44
, and an N+ region
52
. According to Rountre, a positive current associated with an ESD event flows through region
48
to avalanche a PN junction between well
46
and layer
44
. The current flows from layer
44
to region
52
across the PN junction and ultimately to ground to protect an IC from the ESD event. However, a disadvantage of the SCR structure shown in
FIG. 1
is its susceptibility to being accidentally triggered by substrate noise.
In addition, the p-n—p-n path of an SCR device, such as the device shown in
FIG. 1
, is blocked by the insulator layer and shallow trench isolations (STIs) in ICs formed with the SOI CMOS technology. Accordingly, SCR devices have been proposed in an integrated circuit based on the SOI CMOS technology.
FIG. 2
is a reproduction of FIG. 4 of U.S. Pat. No. 6,015,992 to Chatterjee, entitled “Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits.” Chatterjee describes an “SCR-like switch” provided by a first transistor
42
and a second transistor
44
, that are separated from each other by an insulation region
60
. The bistable SCR-like device has two additional lines
62
,
64
to electrically connect the separate transistors.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided an integrated circuit device that includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, and a layer of silicon material, formed over the isolation layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, a second n-type portion contiguous with the second p-type portion, a third p-type portion contiguous with the second n-type portion, and a third n-type portion contiguous with the third p-type portion. The first, second, and third p-type portions and the first, second, and third n-type portions collectively form a rectifier, the first p-type portion and the first n-type portion form a cathode of the rectifier, and the third n-type portion and the third p-type portion form an anode of the rectifier.
In yet another aspect, the second n-type portion includes the third n-type portion and the third p-type portion, each of which being spaced apart from the isolation layer.
In another aspect, the second p-type portion includes a fourth n-type portion formed spaced apart from the first n-type portion, and the first n-type portion and the fourth n-type portion define a source region and a drain region of an NMOS transistor.
In still another aspect, the second n-type portion includes a fourth p-type portion formed spaced apart from the third p-type portion, and the third p-type portion and the fourth p-type portion define a source region and a drain region of a PMOS transistor.
Also in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a rectifier to provide electrostatic discharge protection.
In another aspect, the integrated circuit device further comprises an electrostatic discharge circuit for providing the bias voltage to trigger the rectifier. The electrostatic discharge circuit comprising a first inverter including a first PMOS transistor having a gate, a source region and a drain region, and a first NMOS transistor having a gate, a source region and a drain region, wherein the gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor, and the gate of the p-type MOS transistor is coupled to the drain region of the first PMOS transistor and the drain region of the first NMOS transistor.
In yet another aspect, the electrostatic discharge circuit further comprises a second inverter, including a second PMOS transistor having a gate, a source region and a drain region, and a second NMOS transistor having a gate, a source region and a drain region, wherein the gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor, and the gate of the n-type MOS transistor is coupled to the drain region of the second PMOS transistor and the drain region of the second NMOS transistor.
In still another aspect, the cathode is coupled to at least one diode to prevent the rectifier from being triggered in a non-ESD operation.
Further in accordance with the present invention, there is provided a method for protecting a silicon-on-insulator semiconductor circuit from electrostatic discharge that includes providing an n-type MOS transistor having a source region and a drain region in the silicon-on-insulator circuit, providing a p-type MOS transistor having a source region and a drain region, the p-type MOS transistor being contiguous with the n-type MOS transistor, providing a p-type region contiguous with one of the source region and the drain region of the n-type MOS transistor to form a ca

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