Scoreboarding for DRAM access within a multi-array DRAM device u

Details Scoreboarding for DRAM access within a multi-array DRAM device u Scoreboarding for DRAM access within a multi-array DRAM device u

1996-08-08

2000-02-08

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711149, 711168, 711169, G06F 1200

Patent

active

060237457

ABSTRACT:
A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place. Upon presentation of a row and array, the scoreboard determines if the presented row is currently open, and if so, generates a hit signal that allows an immediate read/write access to the presented row. If the presented row is not open, the present invention generates a miss signal so that the row can be immediately opened before access is allowed. The scoreboard contains a memory unit containing row information for each array in the DRAM. The scoreboard, in addition to other novel features, allows an efficient DRAM configuration allowing dual memory accesses per cycle.

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