Scheme to define laser fuse in dual damascene CU process

Details Scheme to define laser fuse in dual damascene CU process Scheme to define laser fuse in dual damascene CU process

2002-09-10

2004-05-18

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S612000, C438S623000, C438S620000, C438S622000, C438S638000, C438S132000, C438S215000, C438S281000, C257S529000, C257S530000

Reexamination Certificate

active

06737345

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to define a thin copper fuse at a top via opening, in a partially etched, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation.
(2) Description of Related Art
The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 6,235,557 B1 entitled “Programmable Fuse and Method Thereof” granted May 22, 2001 to Manley, shows a copper fuse in a next to last metal interconnect layer. A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. A fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existing mask of the last metal interconnect layer, typically the pad mask. The passivation layer on top of the bond pads is opened to expose the bonding pads. At the same time, a residual oxide window is defined over the fuse. The residual oxide covering the fuse provides for a reliable and reproducible fuse.
U.S. Pat. No. 6,180,503 B1 entitled “Passivation Layer Etching Process for Memory Arrays With Fusible Links” granted Jan. 30, 2000 to Tzeng et al. teaches a copper laser fuse process. A method is described for progressively forming a fuse access openings in integrated circuits which are built with redundancy and use laser trimming to remove and insert circuit sections. The fuses are formed in a polysilicon layer and covered by one or more relatively thin insulative layers. An etch stop is patterned over the fuse in a higher level polysilicon layer or a first metallization layer. Additional insulative layers such as inter-metal dielectric layers are then formed over the etch stop. A first portion of the laser access window is then etched during the via etch for the top metallization level. A laser access window is formed over the fuses.
U.S. Pat. No. 6,033,939 entitled “Method for Providing Electrically Fusible Links In Copper Interconnect” granted Mar. 7, 2000 to Agarwala et al. discloses electrical fuses in copper interconnects with a dual damascene process. A method is provided for the fabrication of fuses within a semiconductor IC structure, which fuses are detectable by a laser pulse or a low voltage electrical pulse typically below 3.5 v to reroute the electrical circuitry of the structure to remove a faulty element. The fuses are formed on the surface of circuitry which is coplanar with a surrounding dielectric such as the circuitry formed by a damascene method. A preferred fuse material is silicon-chrome-oxygen and the preferred circuitry is copper.
U.S. Pat. No. 5,795,819 entitled “Integrated Pad and Fuse Structure For Planar Copper Metallurgy” granted Aug. 18, 1998 to Motsiff et al. shows a semiconductor interconnection consists of a corrosion resistant integrated fuse and a Controlled, Collapse, Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non-copper fuse material is directly connected to copper wiring.
SUMMARY OF THE INVENTION
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to define a thin copper fuse at a top via opening, in a partially etched, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation.
As a background to the current invention, it remains a challenge in dual damascene processing to improve upon the Prior Art conventional methods for fabrication copper laser fuses, which traditionally locate the copper laser fuses in a wiring level, termed an N-2 metal layer, considerably below the surface of the semiconductor substrate. This requires that a very thick layer of dielectric material has to be etched without the benefit of an etch stop and the copper fuse is typically buried in a low dielectric constant material. The low dielectric constant material has poor thermal conductivity, a low glass transition temperature, and poor mechanical stress properties, and thus, tends to be prone to thermal shock, as a laser pulse ablates a copper fuse. However, to relocate laser fuses to an upper surface, top metal wiring level, is a problem since the top metal wiring level is always used for power line wiring, requiring thicker metal, and thus, increases the difficulty to cleanly ablate a thick copper fuse.
The method of the present invention overcomes the problems encountered by the Prior Art methods listed above, and some of the advantages of the present invention:
(a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation,
(b) increases insulating material thickness over the fuse, using better thickness control, and most importantly,
(c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.
Basically, the dual damascene method of the present invention is as follows:
a) defining a via pattern with photoresist and a via photo-mask, for purpose of partially etching exposed via openings, and fully etching exposed fuse openings, which are close to the surface of the substrate
b) partially etching the exposed insulator forming partially etched via openings and fully etched fuse openings, stopping on an etch stop layer
c) defining a trench pattern with photoresist and a trench photo-mask, for purpose of etching exposed trench openings, partially etching trench/via openings, and completely covering fuse openings with protective photoresist
d) fully etching the exposed insulator forming fully etched trench openings, completing a partial etch of the trench/via openings, while protecting fuse openings
e) etching through a bottom liner or thin insulator layer to breakthrough that layer to make electrical contact to a lower metal wiring layer, before stripping the trench patterned photoresist
f) depositing a diffusion barrier and copper seed layer in the trench openings, in the trench/via openings and in the laser via openings
g) plating copper over the copper seed layer
h) chemical mechanical polishing the excess material, excess copper and planarizing the surface, forming inlaid copper interconnects, contact vias and copper laser via fuses
Thus, forming copper laser via fuses, which are fusible links, delectable by laser pulses, for the purpose of rerouting various components on an integrated circuit, the fuses being formed in a dual damascene trench/via process. Furthermore, openings are formed for a laser access window to the via fuses by defining openings in insulators over the via fuses. Through the laser access window, laser radiation enters through the access window for laser ablation of the delectable, copper laser via fuses, which are fusible links.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.


REFERENCES:
patent: 5321300 (1994-06-01), Usuda et al.
patent: 5759906 (1998-06-01), Lou
patent: 5795819 (1998-08-01), Motsiff et al.
patent: 6033939 (2000-03-01), Agarwala et al.
patent: 6111301 (2000-08-01), Stamper
patent: 6114231 (2000-09-01), Chen et al.
patent: 6180503 (2001-01-01), Tzeng et al.
patent: 6235557 (2001-05-01), Manley
patent: 6559042 (2003-05-01), Barth et al.
patent: 6645781 (2003-11-01), Jiang et al.
patent: 6667533 (2003-12-01), Daubenspeck et al.
patent: 2003/0003703 (2003-01-01), Barth et al.
patent: 2003/0038339 (2003-02-01), Mori

Affiliated with

Also associated with

Rating

Scheme to define laser fuse in dual damascene CU process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scheme to define laser fuse in dual damascene CU process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheme to define laser fuse in dual damascene CU process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3201461