Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-05
2002-04-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S253000
Reexamination Certificate
active
06373090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to FET semiconductor devices and more particularly to capacitor structures formed on FET semiconductor devices.
2. Description of Related Art
U.S. Pat. No. 5,045,899 of Arimoto for “Dynamic Random Access Memory Having Stacked Capacitor Structure” shows a DRAM in which a plurality of word-lines (WL) and a plurality of bit-lines are arranged to orthogonally intersect each other. Memory cells are arranged in a direction intersecting the bit-lines. Capacitors of the memory cells are arranged between the adjacent bit-lines. On a silicon substrate, the bit-line is formed substantially at the same height with the word-line and positioned lower than the top of the capacitor. The arrangement of the capacitors between the adjacent bit-lines allows reduction in the inter-bit-line capacitance.
U.S. Pat. No. 5,107,459 of Chu et al. for “Stacked Bit-Line Architecture for High Density Cross-Point Memory Cell Array” shows a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other.
U.S. Pat. No. 5,449,934 of Shono et al. for “Semiconductor Memory Device and Process” shows a DRAM memory device with a COB (Capacitor Over Bit-line) structure with a Bitline below Capacitor arrangement. The storage capacitor contact passes through a bit-line, a drain and source can be arranged symmetrically with a word-line, like a memory cell with a bit-line below-storage-capacitor organization cell.
FIGS. 3A and 3B
provide a comparison of prior art COB (FIG.
3
A), and CUB (
FIG. 3B
) designs for DRAM cells.
The COB design of
FIG. 3A
shows the bit-lines BLA below the capacitor C
1
with a high degree of coupling capacity C
CA
. The CUB design of
FIG. 3B
shows the bit-lines BLB above the capacitor C
1
with a high degree of coupling capacity C
CB
, roughly equivalent to coupling capacity C
CA
.
The process flow for the COB design for 8F
2
DRAM cells of Kohyama et al. is described as follows:
8F
2
DRAM Cell with COB for 0.18 Micrometer and Beyond
An article by Kohyama et al., “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond”, 1997 Symposium on VLSI Technology Digest of Technical papers Paper 3A-1, pp. 17-18 (1997) describes an 0.18 micrometer DRAM technology and beyond, the cell on folded-bit-line architecture has minimum cell of 8F
2
.
FIGS. 1A-1C
show the first part of a prior art process flow of the Kohyama et al. with a plan view and cross-sectional layouts of the process flow, from isolation to self-aligned polysilicon (Poly) plug formation.
For simple patterns, F represents the minimum feature by a unit square of F×F dimensions, where F is the minimum feature size limited by lithography. There are several key techniques must met in order to achieve an 8F
2
cell. 1. The mask pattern must be simple to get a larger range of focus depth. 2. Self-aligned node contact to the bit-line must be realized. 3. Planarization by CMP (Chemical Mechanical Polishing) is used extensively.
Kohyama et al. suggests a fabrication method for a COB 8F
2
DRAM cell with all three of the above listed features as shown in
FIGS. 1A and 1B
.
1. STI Isolation
The first part of the prior art process is described with reference to
FIGS. 1A-1C
for cell area, with the process starting with the well-known Shallow Trench Isolation (STI) process as shown in silicon oxide regions STI surrounding active regions AA in the silicon semiconductor substrate of device
10
which is a fragment of a semiconductor wafer. The depth of the trenches is approximately 0.2 &mgr;m. Illustrations of the process in the periphery area are not shown.
2. Well Formation
Next follows formation of an N-well in the periphery which is not shown and a P-well
11
in the silicon semiconductor substrate of device
10
. The process employed uses well known process steps for implantation of phosphorus and boron respectively in a selective process.
3. Transistor Gate Formation
Gate Oxide/Gate Stack (e.g. polysilicon/WSi
2
/Si
3
N
4
deposit)
Then a gate oxide layer GX with a thickness of about 60 Å (not to scale in
FIG. 1B
) is grown on the surface of P-well
11
. with gate oxide layer GX grown above isolation regions STI. Then polycide gate stack material layers of a first polysilicon layer
14
, tungsten silicide (WSi
2
) layer
16
and first silicon nitride (Si
3
N
4
) dielectric layer
18
are deposited.
Gate Stack Mask/Etch (Word Lines (WL) and transistors)
Then a set of transistor gate electrode stacks for word lines in an array and transistors in the periphery are defined by masking and etching to form transistor gate electrode stacks (as shown Word Lines WL
1
, WL
2
, WL
3
and WL
4
in
FIGS. 1A and 1B
and the layers
14
,
16
and
18
shown in FIG.
1
B). SiO
2
/Si
3
N
4
Deposition (Deposit spacer layers)
Next, spacer layers including a blanket layer of silicon oxide spacer layer SP and a blanket second silicon nitride (Si
3
N
4
) spacer layer are deposited.
Peripheral Area N+, P+, S/D Mask/Implant, RTA Anneal
A mask is used to open the peripheral area. Then the second Si
3
N
4
spacer layer is etched to form spacers SP for the transistors in the periphery area. Please notice that the silicon nitirde (Si
3
N
4
) spacer layer remains on the cell at this stage of the process.
Transistor LDD regions and source/drain regions, etc. (not shown because they are in the periphery area and are well known process steps) are defined and formed by implanting NLDD, N+, PLDD, and P+ regions selectively followed by a RTA (Rapid Thermal Anneal) annealing step for removing defects resulting from implantation steps.
BPSG Deposition, CMP
Next a BPSG glass layer BG
1
is deposited followed by a thermal reflow for the BPSG layer BG
1
. Next follows a CMP (Chemical Mechanical Polishing) step of planarizing the BPSG glass layer BG
1
surface. The CMP step will stop on the top of the second nitride (spacer) layer in the cell area.
4. Self-aligned Polysilicon plug formation SAC Mask/Etch (Stop on Silicon Nitride)
Next, plug holes through layer BG
1
are prepared for formation of a lower set of self-aligned polysilicon plugs PL
1
which are to be formed later. The plug holes are made by using a SAC (Self-Aligned Contact) mask, which is the same as the active area (AA) mask, but shifted one F as shown in FIG.
1
A and described by Kohyama et al. (above), and etching the BPSG layer BG
1
on those open areas of the SAC mask with a wet etchant. This wet etching step stops at the second Si
3
N
4
(spacer) layer. Notice that the SAC mask is the same as the AA mask but is shifted by one F, and the entire periphery area is protected.
Cell Silicon Nitride Spacer Etch (Stop on Oxide)
Then, the second Si
3
N
4
(spacer) layer is etched to form spacers for the cells by stopping on the silicon oxide spacer layer SP. Then the SAC contact mask photoresist is removed and the wafer
10
is cleaned.
NLDD Ion Implant
Next there is a blank NLDD ion implant for the cell node junctions shown as NLDD regions in
FIGS. 1B and 1C
.
Deposition of Doped Polysilicon and Polysilicon CMP
Then after a wet dip of the silicon oxide, a blanket N-type doped second polysilicon (plug) layer PL
1
covering device
10
is deposited filling the plug holes formed in the SAC Mask/Etch above. Then the doped second polysilicon layer is polished by CMP which stops at the first silicon nitride layer
18
to finish formation of plugs PL
1
. The polysilicon plugs PL
1
are now in contact with the silicon
11
beneath them and plugs PL
1
serve the function as an extension (electrically) of the silicon substrate at the node contacts and the bit-line contacts.
Deposition of First IPO layer
Next a blanket first Inter-Polysilicon, silicon Oxide (IPO) dielectric layer IP
1
is deposited over device
10
. As seen in the cross-section in
FIG. 1B
, layer IP
1
covers the plugs PL
1
, and the first Silicon Nitride (Si
3
N
4
) layer
18
. As seen in
Ackerman Stephen B.
Jones, III Graham S.
Le Thao P.
Nelms David
Saile George O.
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