Scheduling logic on a programmable device implemented using...

Details Scheduling logic on a programmable device implemented using... Scheduling logic on a programmable device implemented using...

2004-11-16

2008-08-05

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C710S023000, C711S100000, C712S023000

Reexamination Certificate

active

07409670

ABSTRACT:
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acceleration. Dedicated ports are generated to allow the hardware accelerator to handle pointer referencing and dereferencing. A hardware accelerator is generated to perform pipelined processing of instructions. The number of stages implemented for pipelined processing is at least partially dependent on the latency associated with accessing secondary components.

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